Abstract: In an example, an apparatus may have a controller to be coupled to a host, an interface component coupled to the controller, and a plurality of memory devices coupled to the interface component. The interface component may be to cause a memory device of the plurality of memory devices to perform an operation in response to a command from the controller.

Abstract: In an example, an apparatus may have a controller to be coupled to a host, an interface component coupled to the controller, and a plurality of memory devices coupled to the interface component. The interface component may be to cause a memory device of the plurality of memory devices to perform an operation in response to a command from the controller.

Abstract: In an example, an apparatus may have a controller to be coupled to a host, an interface component coupled to the controller, and a plurality of memory devices coupled to the interface component. The interface component may be to cause a memory device of the plurality of memory devices to perform an operation in response to a command from the controller.

Abstract: In an example, an apparatus may have a controller to be coupled to a host, an interface component coupled to the controller, and a plurality of memory devices coupled to the interface component. The interface component may be to cause a memory device of the plurality of memory devices to perform an operation in response to a command from the controller.

Abstract: In an example, an apparatus may have a controller to be coupled to a host, an interface component coupled to the controller, and a plurality of memory devices coupled to the interface component. The interface component may be to cause a memory device of the plurality of memory devices to perform an operation in response to a command from the controller.

Abstract: In an example, an apparatus may have a controller to be coupled to a host, an interface component coupled to the controller, and a plurality of memory devices coupled to the interface component. The interface component may be to cause a memory device of the plurality of memory devices to perform an operation in response to a command from the controller.

Abstract: In an example, an apparatus may have a controller to be coupled to a host, an interface component coupled to the controller, and a plurality of memory devices coupled to the interface component. The interface component may be to cause a memory device of the plurality of memory devices to perform an operation in response to a command from the controller.

Abstract: In a distributed switch architecture, each incoming signal is sliced into a plurality of sub-signals. A checksum function is applied to subsets of data in each sub-signal to generate and add a checkbit to the sub-signal for each subset of data. Two copies of the augmented sub-signal are routed in parallel through redundant portions of the distributed switch fabric. Only one of the resulting routed sub-signals is selected for use in generating the corresponding outgoing signal, which is generated by combining data from selected routed sub-signals corresponding to all of the original sub-signals. Checksum analysis is performed on the two routed sub-signals to determine if a fault has occurred. If a fault is detected in the routed sub-signal currently being selected for use in generating the outgoing signal, the selection is changed so that the other routed sub-signal is used.