Abstract: A high data width accelerator, comprising computer instructions for calculating at least a portion of a trace-back during a trellis computation, wherein the calculation allows faster trace-back

Abstract: A digital signal processor for decoding Trellis based channel encoding stages based on radix-4 stages comprising means for rearranging the input and output data in Radix-4 Viterbi decoding to make inter-stage Trellis data movement suitable for use in the digital signal processor.

Abstract: A wireless communications base station (10) having a digital bit modulation function (72) is disclosed. The bit modulation function (72) may be realized by a software routine executable by a programmable device such as a digital signal processor (40), or alternatively by dedicated logic circuitry. The bit modulation function (72) receives a datastream corresponding to the payload, and a scrambling code, each of which include an in-phase component and a quadrature component. The bit modulation function (72) corresponds to a split adder (94) that performs a Gray Code addition of corresponding bits of the in-phase and quadrature data components with corresponding bits of the in-phase and quadrature scrambling code components. The result is a combined in-phase bit and a combined quadrature bit for each bit position in the datastream. The Gray Code addition takes the place of a complex multiplication, thus saving significant processing capacity or reducing circuit complexity.

Abstract: A wireless communications device is disclosed, in which certain digital coding functions are realized according to a modified multiplier architecture. The device includes an encode and modulate function within which convolutional coding function is provided. The convolutional coding function may be realized as a modified parallel multiplier, in which carries among adder units are ignored or not generated. The datastream is applied to the multiplier as the multiplicand, while successive sets of code generator polynomial coefficients are applied as a multiplier. Carry-in and carry-out bits among the adder units are blocked in a coding mode, but passed in a multiplier mode. A similar arrangement of a modified parallel multiplier circuit may be used in generating a scrambling code that is applied prior to transmission.

Abstract: A wireless communications device (30) is disclosed, in which certain digital coding functions are realized according to a modified multiplier architecture. The device (30) includes an encode and modulate function (54) within which convolutional coding function (60) is provided. According to one alternative, convolutional coding function (60) is realized by way of a modified parallel multiplier (90), in which carries among adder units are ignored or not generated. The datastream x(k) is applied to the multiplier as the multiplicand, while successive sets of code generator polynomial coefficients are applied as a multiplier. The parallel multiplier (90) is modified in that carry-in and carry-out bits among the adder units are selectably blocked in a coding mode, but passed in a multiplier mode. A similar arrangement of a modified parallel multiplier circuit (90′) may be used in generating a scrambling code that is applied prior to transmission.

Abstract: A wireless communications base station (10) having a digital bit modulation function (72) is disclosed. The bit modulation function (72) may be realized by a software routine executable by a programmable device such as a digital signal processor (40), or alternatively by dedicated logic circuitry. The bit modulation function (72) receives a datastream corresponding to the payload, and a scrambling code, each of which include an in-phase component and a quadrature component. The bit modulation function (72) corresponds to a split adder (94) that performs a Gray Code addition of corresponding bits of the in-phase and quadrature data components with corresponding bits of the in-phase and quadrature scrambling code components. The result is a combined in-phase bit and a combined quadrature bit for each bit position in the datastream. The Gray Code addition takes the place of a complex multiplication, thus saving significant processing capacity or reducing circuit complexity.

Abstract: There is disclosed a system and method for demodulating an analog signal using digital conversion of the analog signal. In one embodiment the incoming modulated signal is digitally sampled and a calculation is made as to both the short term and long term energy of the digitized version of the analog signal. The deviation between the short and long term energy levels is used to determine the amount of modulation of the incoming analog signal. An analog demodulated signal is then reconstructed from the digitized deviation calculations. In an alternate embodiment, a digital signal processor is used to derive the demodulated signal.

Abstract: A digital signal processor includes a parallel multiplier having first and second input ports, in which the first input port has conductors for many more bits than does the second input port. First and second data selectors are connected respectively to the first and second ports to enable data from a RAM and data from a ROM to be selectively applied to either or both ports, directly or via a pipe-line register. The second data selector can select two or more groups of bits from the RAM or ROM to enable the multiplier to multiply numbers having more bits than can be input at the second input port at one time. A third data selector is connected to the output port of the multiplier and is capable of shifting the product received relative to the output conductors to effect multiplication by powers of two. A particular application of the processor is for processing pulse coded speech signals.