Abstract: A communication system is dynamically configured to use some or all of the communication channel bandwidth. Regions of the communication channel are prioritized, and bandwidth is allocated in accordance with priorities and requested data rate.

Abstract: Techniques for performing a bit rake instruction in a programmable processor. The bit rake instruction extracts an arbitrary pattern of bits from a source register, based on a mask provided in another register, and packs and right justifies the bits into a target register. The bit rake instruction allows any set of bits from the source register to be packed together.

Abstract: Techniques for performing a bit rake instruction in a programmable processor. The bit rake instruction extracts an arbitrary pattern of bits from a source register, based on a mask provided in another register, and packs and right justifies the bits into a target register. The bit rake instruction allows any set of bits from the source register to be packed together.

Abstract: A simple fast and robust echo canceller for both synchronous and asynchronous multicarrier transceiver systems. A first residual time domain echo component is separated from a receive signal in a first frame and a second residual time domain echo component is separated from a receive signal in the next consecutive frame. The first and second residual time domain echo components from consecutive frames are combined to obtain a combined residual time domain echo component. The combined residual time domain echo component is used to adaptively update coefficients in a transfer function representing an estimate of the echo channel in the multicarrier transceiver system. The separation of the echo components from the receive signal eliminates dependence on the receive signal so that convergence is substantially faster and not signal dependent. Performance of the echo canceller is virtually independent of the receive signal and allows reliable tracking of changes in the echo channel over time.

Abstract: An echo canceler (34) includes a summing device (104) that subtracts a correction signal from a received signal, the difference of which represents the far-end signal with an error component. Instead of adapting its coefficients using the output of the summing device (104), the echo canceler (34) uses the difference between the input and output of a decision device (108) as an estimate of the error component alone. The estimate of the error component is then used to adapt the coefficients according to the adaptive least mean squares (LMS) algorithm. In one embodiment, the decision device (108) forms discrete multi-tone symbols based on the equalized output of the summing device. In this embodiment, the echo canceler (34) performs an inverse of the equalization step efficiently by replacing a division operation with a multiply operation and a corresponding power-of-two shift operation.

Abstract: Techniques for performing a bit rake instruction in a programmable processor. The bit rake instruction extracts an arbitrary pattern of bits from a source register, based on a mask provided in another register, and packs and right justifies the bits into a target register. The bit rake instruction allows any set of bits from the source register to be packed together.

Abstract: A method and apparatus for performing DMT frame synchronization in an ADSL system begins by providing a training signal (82) to a receiver of the ADSL system (34). The training signal (82) is processed to result in a desired impulse response. The impulse response is used to reduce inter-symbol interference between time-adjacent DMT frames (100-108). The desired impulse response is used to calculate a frame misalignment value (.DELTA.T). The frame misalignment value (.DELTA.T) of the desired impulse response (84) is then utilized to adjust an internal counter of the receiver to perform frame alignment. The use of the training signal (82) and impulse response (84) to provide for both intersymbol interference reduction (FIG. 5) and frame synchronization (FIG. 8) provides for fast ADSL initialization.

Abstract: A communications system 10 having an Asymmetric Digital Subscriber Line (ADSL) transceiver (24) is provided which may be configured either as a central office or a remote terminal in a system. The transceiver (24) operates in a listen/report idle state to report line activity to a host processor (22) prior to being configured as a central office or remote terminal. The host processor configures the transceiver (24) as a central office, remote terminal, or as otherwise specified based on the line activity.

Abstract: A transceiver (5) for an asymmetric communication system such as asymmetric digital subscriber line (ADSL) includes a configuration register (71) defining operation at either a central office (CO) or a remote terminal (RT). The configuration register (71) includes a control bit (72) for selecting either CO or RT mode. The transceiver (5) includes a signal processing module (70) configured according to the state of the control bit (72). For example, a digital interface (70) converts transmit data into transmit symbols and converts received symbols into receive data. The digital interface (70) uses a large memory (158) as a buffer in the transmit path and a small memory (160) as a buffer in the receive path in CO mode. In RT mode, the digital interface (70) uses the small memory (160) in the transmit path and the large memory (158) in the receive path. The selective configuration allows a single integrated circuit to be used in both CO and RT equipment.

Abstract: A host processor (22) in a communication system (10) identifies a level of program visibility for reporting predetermined activation state changes, and signals a communications transceiver (24) to begin an initialization process. The communications transceiver (24) begins executing a series of states (51-55, 61-64) for initializing the communication system (10). A determination is made by the transceiver (24) whether a state change has occurred. A state change is identified and reported to a host processor (22) based on the program visibility select level.

Abstract: A flexible asymmetrical digital subscriber line (ADSL) transmitter is able to operate simultaneously with integrated services digital network (ISDN) terminal equipment (TE) using a common telephone line (18). The ADSL transmitter changes the frequency content of a frequency-encoded ADSL signal (104) so that its frequency content does not overlap the frequency content of the ISDN TE signal. A corresponding ADSL receiver located within a central office (CO) adapts to the changed frequency content, allowing the ADSL signal to be transmitted over the telephone line without substantial loss of signal integrity. In one embodiment, an ADSL transmitter (100) converts ADSL symbols making up the frequency-encoded ADSL signal (104) into a corresponding time domain signal. The transmitter (100) then interpolates the time domain signal and high pass filters the interpolated signal. This high pass filtered signal is then converted to analog form, bandpass filtered, and driven onto the telephone line (18).

Abstract: An ADSL receiver (200) receives an upstream modified ADSL signal and an ISDN signal from a remote terminal (32) on a twisted-pair copper wire (18). An ADSL transmitter (100) of the remote terminal (32) transmits the ADSL signal in a frequency range above an ISDN frequency range so that the ADSL signal does not overlap the frequency range of the ISDN signal. In one embodiment, the ADSL receiver (200) includes a band pass filter (201), an analog-to-digital converter (203), a decimator (205), a fast Fourier transform (210), and a digital signal processor (212). The decimator (205) converts the ADSL signal back to base band, thus allowing an ADSL signal source to simultaneously utilize the telephone line with an ISDN signal source, without significantly reducing ADSL throughput.