Patents by Inventor Peter Rabkin

Peter Rabkin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8557654
    Abstract: A punch-through diode and method of fabricating the same are disclosed herein. The punch-through diode may be used as a steering element in a memory device having a reversible resistivity-switching element. For example, a memory cell may include a reversible resistivity-switching element in series with a punch-through diode. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. In other words, the ratio of Ion/Ioff is high. Therefore, the punch-through diode is compatible with bipolar switching in cross-point memory arrays having resistive switching elements.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: October 15, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Peter Rabkin, Andrei Mihnea
  • Publication number: 20130264631
    Abstract: A three dimensional memory device including a substrate and a semiconductor channel. At least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of the substrate. The device also includes at least one charge storage region located adjacent to semiconductor channel and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level. Each of the plurality of control gate electrodes includes a first edge surface which is substantially free of silicide, the first edge surface facing the semiconductor channel and the at least one charge storage region and a silicide located on remaining surfaces of the control gate electrode.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 10, 2013
    Applicant: SanDisk Technologies, Inc.
    Inventors: Johann Alsmeier, Peter Rabkin
  • Publication number: 20130234099
    Abstract: Non-volatile storage elements having a reversible resistivity-switching element and techniques for fabricating the same are disclosed herein. The reversible resistivity-switching element may be formed by depositing an oxygen diffusion resistant material (e.g., heavily doped Si, W, WN) over the top electrode. A trap passivation material (e.g., fluorine, nitrogen, hydrogen, deuterium) may be incorporated into one or more of the bottom electrode, a metal oxide region, or the top electrode of the reversible resistivity-switching element. One embodiment includes a reversible resistivity-switching element having a bi-layer capping layer between the metal oxide and the top electrode. Fabricating the device may include depositing (un-reacted) titanium and depositing titanium oxide in situ without air break. One embodiment includes incorporating titanium into the metal oxide of the reversible resistivity-switching element.
    Type: Application
    Filed: March 21, 2013
    Publication date: September 12, 2013
    Applicant: SANDISK 3D LLC
    Inventors: Deepak C. Sekar, Franz Kreupl, Raghuveer S. Makala, Peter Rabkin, Chu-Chen Fu, Tong Zhang
  • Patent number: 8520424
    Abstract: A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: August 27, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Franz Kreupl, Abhijit Bandyopadhyay, Yung-Tin Chen, Chu-Chen Fu, Wipul Pemsiri Jayasekara, James Kai, Raghuveer S. Makala, Peter Rabkin, George Samachisa, Jingyan Zhang
  • Publication number: 20130148404
    Abstract: In some aspects, a memory cell is provided that includes a steering element and a metal-insulator-metal (“MIM”) stack coupled in series with the steering element. The MIM stack includes a first dielectric material layer and a second dielectric material layer disposed on the first dielectric material layer, without a metal or other conductive layer disposed between the first dielectric material layer and the second dielectric material layer. Numerous other aspects are provided.
    Type: Application
    Filed: December 8, 2011
    Publication date: June 13, 2013
    Inventors: Abhijit Bandyopadhyay, Roy E. Scheuerlein, Peter Rabkin
  • Patent number: 8462580
    Abstract: A memory system includes a plurality of non-volatile storage elements that each comprise a diode (or other steering device) in series with reversible resistance-switching material. One or more circuits in the memory system program the non-volatile storage elements by changing the reversible resistance-switching material of one or more non-volatile storage elements to a first resistance state. The memory system can also change the reversible resistance-switching material of one or more of the non-volatile storage elements from the first resistance state to a second resistance state by applying one or more pairs of opposite polarity voltage conditions (e.g., pulses) to the respective diodes (or other steering devices) such that current flows in the diodes (or other steering devices) without operating the diodes (or other steering devices) in breakdown condition.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: June 11, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Peter Rabkin, George Samachisa, Roy E. Scheuerlein
  • Publication number: 20130127011
    Abstract: Passive devices such as resistors and capacitors are provided for a 3D non-volatile memory device. In a peripheral area of a substrate, a passive device includes alternating layers of a dielectric such as oxide and a conductive material such as heavily doped polysilicon or metal silicide in a stack. The substrate includes one or more lower metal layers connected to circuitry. One or more upper metal layers are provided above the stack. Contact structures extend from the layers of conductive material to portions of the one or more upper metal layers so that the layers of conductive material are connected to one another in parallel, for a capacitor, or serially, for a resistor, by the contact structures and the at least one upper metal layer. Additional contact structures can connect the circuitry to the one or more upper metal layers.
    Type: Application
    Filed: November 21, 2011
    Publication date: May 23, 2013
    Inventors: Masaaki Higashitani, Peter Rabkin
  • Publication number: 20130130468
    Abstract: A method for fabricating passive devices such as resistors and capacitors for a 3D non-volatile memory device. In a peripheral area of a substrate, alternating layers of a dielectric such as oxide and a conductive material such as heavily doped polysilicon or metal silicide are provided in a stack. The substrate includes one or more lower metal layers connected to circuitry. One or more upper metal layers are formed above the stack. Contact structures are formed which extend from the layers of conductive material to portions of the one or more upper metal layers so that the layers of conductive material are connected to one another in parallel or serially by the contact structures and the at least one upper metal layer. Additional contact structures can connect the circuitry to the one or more upper metal layers. The passive device can be fabricated concurrently with a 3D memory array using common processing steps.
    Type: Application
    Filed: November 21, 2011
    Publication date: May 23, 2013
    Inventors: Masaaki Higashitani, Peter Rabkin
  • Publication number: 20130130495
    Abstract: A method for fabricating a metal silicide interconnect in a stacked 3D non-volatile memory array. A stack of alternating layers of undoped/lightly doped polysilicon and heavily doped polysilicon is formed on a substrate. Memory holes are etched in cell areas of the stack while an interconnect area is protected. Slits are etched in the cell areas and the interconnect areas. A wet etch is performed via the slits or the memory holes in the cell area to remove portions of the undoped/lightly doped polysilicon layers in the cell area, and dielectric is deposited. Silicidation transforms portions of the heavily doped polysilicon layers in the cell area to metal silicide, and transforms portions of the heavily doped and undoped/lightly doped polysilicon layers in the interconnect area to metal silicide. The metal silicide interconnect can be used for routing power and control signals from below the stack to above the stack.
    Type: Application
    Filed: November 21, 2011
    Publication date: May 23, 2013
    Inventors: Masaaki Higashitani, Peter Rabkin
  • Publication number: 20130126957
    Abstract: A stacked non-volatile memory cell array include cell areas with rows of vertical columns of NAND cells, and an interconnect area, e.g., midway in the array and extending a length of the array. The interconnect area includes at least one metal silicide interconnect extending between insulation-filled slits, and does not include vertical columns of NAND cells. The metal silicide interconnect can route power and control signals from below the stack to above the stack. The metal silicide interconnect can also be formed in a peripheral region of the substrate. Contact structures can extend from a terraced portion of the interconnect to at least one upper metal layer, above the stack, to complete a conductive path from circuitry below the stack to the upper metal layer. Subarrays can be provided in a plane of the array without word line hook-up and transfer areas between the subarrays.
    Type: Application
    Filed: November 21, 2011
    Publication date: May 23, 2013
    Inventors: Masaaki Higashitani, Peter Rabkin
  • Patent number: 8435831
    Abstract: Non-volatile storage elements having a reversible resistivity-switching element and techniques for fabricating the same are disclosed herein. The reversible resistivity-switching element may be formed by depositing an oxygen diffusion resistant material (e.g., heavily doped Si, W, WN) over the top electrode. A trap passivation material (e.g., fluorine, nitrogen, hydrogen, deuterium) may be incorporated into one or more of the bottom electrode, a metal oxide region, or the top electrode of the reversible resistivity-switching element. One embodiment includes a reversible resistivity-switching element having a bi-layer capping layer between the metal oxide and the top electrode. Fabricating the device may include depositing (un-reacted) titanium and depositing titanium oxide in situ without air break. One embodiment includes incorporating titanium into the metal oxide of the reversible resistivity-switching element.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: May 7, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Deepak C. Sekar, Franz Kreupl, Raghuveer Makala, Peter Rabkin
  • Patent number: 8355271
    Abstract: A memory system includes a plurality of non-volatile storage elements that each comprise a diode (or other steering device) in series with reversible resistance-switching material. One or more circuits in the memory system program the non-volatile storage elements by changing the reversible resistance-switching material of one or more non-volatile storage elements to a first resistance state. The memory system can also change the reversible resistance-switching material of one or more of the non-volatile storage elements from the first resistance state to a second resistance state by applying one or more pairs of opposite polarity voltage conditions (e.g., pulses) to the respective diodes (or other steering devices) such that current flows in the diodes (or other steering devices) without operating the diodes (or other steering devices) in breakdown condition.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: January 15, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Peter Rabkin, George Samachisa, Roy E. Scheuerlein
  • Patent number: 8288219
    Abstract: A stack of two polysilicon layers is formed over a semiconductor body region. A DDD implant is performed to form a DDD source region in the semiconductor body region along a source side of the polysilicon stack but not along a drain side of the polysilicon stack. Off-set spacers are formed along opposing side-walls of the polysilicon stack. A source/drain implant is performed to form a drain region in the semiconductor body region along the drain side of the polysilicon stack and to form a highly doped region within the DDD source region such that the extent of an overlap between the polysilicon stack and each of the drain region and the highly doped region is inversely dependent on a thickness of the off-set spacers, and a lateral spacing directly under the polysilicon stack between adjacent edges of the DDD source region and the highly doped region is directly dependent on the thickness of the off-set spacers.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: October 16, 2012
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Peter Rabkin, Hsingya Arthur Wang, Kai-Cheng Chou
  • Publication number: 20120145984
    Abstract: A punch-through diode and method of fabricating the same are disclosed herein. The punch-through diode may be used as a steering element in a memory device having a reversible resistivity-switching element. For example, a memory cell may include a reversible resistivity-switching element in series with a punch-through diode. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. In other words, the ratio of Ion/Ioff is high. Therefore, the punch-through diode is compatible with bipolar switching in cross-point memory arrays having resistive switching elements.
    Type: Application
    Filed: December 13, 2010
    Publication date: June 14, 2012
    Inventors: Peter Rabkin, Andrei Mihnea
  • Publication number: 20120120710
    Abstract: A memory system includes a plurality of non-volatile storage elements that each comprise a diode (or other steering device) in series with reversible resistance-switching material. One or more circuits in the memory system program the non-volatile storage elements by changing the reversible resistance-switching material of one or more non-volatile storage elements to a first resistance state. The memory system can also change the reversible resistance-switching material of one or more of the non-volatile storage elements from the first resistance state to a second resistance state by applying one or more pairs of opposite polarity voltage conditions (e.g., pulses) to the respective diodes (or other steering devices) such that current flows in the diodes (or other steering devices) without operating the diodes (or other steering devices) in breakdown condition.
    Type: Application
    Filed: November 17, 2010
    Publication date: May 17, 2012
    Inventors: Peter Rabkin, George Samachisa, Roy E. Scheuerlein
  • Publication number: 20120120711
    Abstract: A memory system includes a plurality of non-volatile storage elements that each comprise a diode (or other steering device) in series with reversible resistance-switching material. One or more circuits in the memory system program the non-volatile storage elements by changing the reversible resistance-switching material of one or more non-volatile storage elements to a first resistance state. The memory system can also change the reversible resistance-switching material of one or more of the non-volatile storage elements from the first resistance state to a second resistance state by applying one or more pairs of opposite polarity voltage conditions (e.g., pulses) to the respective diodes (or other steering devices) such that current flows in the diodes (or other steering devices) without operating the diodes (or other steering devices) in breakdown condition.
    Type: Application
    Filed: November 17, 2010
    Publication date: May 17, 2012
    Inventors: Peter Rabkin, George Samachisa, Roy E. Scheuerlein
  • Publication number: 20110310655
    Abstract: A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.
    Type: Application
    Filed: June 9, 2011
    Publication date: December 22, 2011
    Inventors: Franz Kreupl, Abhijit Bandyopadhyay, Yung-Tin Chen, Chu-Chen Fu, Wipul Pemsiri Jayasekara, James Kai, Raghuveer S Makala, Peter Rabkin, George Samachisa, Jingyan Zhang
  • Publication number: 20110227026
    Abstract: Non-volatile storage elements having a reversible resistivity-switching element and techniques for fabricating the same are disclosed herein. The reversible resistivity-switching element may be formed by depositing an oxygen diffusion resistant material (e.g., heavily doped Si, W, WN) over the top electrode. A trap passivation material (e.g., fluorine, nitrogen, hydrogen, deuterium) may be incorporated into one or more of the bottom electrode, a metal oxide region, or the top electrode of the reversible resistivity-switching element. One embodiment includes a reversible resistivity-switching element having a bi-layer capping layer between the metal oxide and the top electrode. Fabricating the device may include depositing (un-reacted) titanium and depositing titanium oxide in situ without air brake. One embodiment includes incorporating titanium into the metal oxide of the reversible resistivity-switching element.
    Type: Application
    Filed: November 9, 2010
    Publication date: September 22, 2011
    Inventors: Deepak C. Sekar, Franz Kreupl, Raghuveer Makala, Peter Rabkin, Chu-Chen Fu, Tong Zhang
  • Patent number: 7969011
    Abstract: A metal-insulator diode is disclosed. In one aspect, the metal-insulator diode comprises first and second electrode and first and second insulators arraigned as follows. An insulating region has a trench formed therein. The trench has a bottom and side walls. The first electrode, which comprises a first metal, is on the side walls and over the bottom of the trench. A first insulator has a first interface with the first electrode. At least a portion of the first insulator is within the trench. A second insulator has a second interface with the first insulator. At least a portion of the second insulator is within the trench. The second electrode, which comprises a second metal, is in contact with the second insulator. The second electrode at least partially fills the trench.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: June 28, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Deepak C. Sekar, Tanmay Kumar, Peter Rabkin, Er-Xuan Ping, Xiying Chen
  • Patent number: 7793238
    Abstract: Various approaches for improving an integrated circuit layout. In one approach, a tree-type hierarchical layout representation of the circuit design is traversed. At each block visited during the traversing, a process determines whether there exists an improvement opportunity for each cell associated with the block. In response to determining that an improvement opportunity exists for a cell of a first block of the plurality of blocks, the process determines whether a modification to the cell satisfies one or more rules for every other block of the block type of the first block in the hierarchical representation. If the rules are satisfied, the modification is stored. Otherwise, the modification is discarded.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: September 7, 2010
    Assignee: Xilinx, Inc.
    Inventors: Peter Rabkin, Zhiyuan Wu, Min-Hsing Peter Chen, Jane W. Sowards, Michael J. Hart, Min-Fang Ho