Patents by Inventor Peter Ralph Jaeger

Peter Ralph Jaeger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System for and method of connecting a hardware modeling element to a hardware modeling system
    Patent number: 6148275
    Abstract: An improved system or and method of connecting a hardware modeling element to the pin electronics circuitry of a hardware modeling system, with the improved system having circuitry and structures that will allow it to be connected to a hardware modeling system that is powered, circuitry to indicate to the pin electronics circuitry that the improved system is connected to it, circuitry to identify the hardware modeling element supported by the improved system to the hardware modeling system, circuitry to indicate to the hardware modeling system when the hardware modeling element is initialized so evaluation of it by the hardware modeling system can commence, circuitry to generate selectable supply voltages for the powering the hardware modeling element, and a hardware modeling element connector that will allow the connection of a family of hardware modeling elements to the same connector without the need to change the connector.
    Type: Grant
    Filed: August 28, 1997
    Date of Patent: November 14, 2000
    Assignee: Synopsys, Inc.
    Inventors: Mark Stanley Papamarcos, Andrew Jefferson Read, Wayne Phillip Heideman, Robert Kristianto Mardjuki, Robert Kimberly Couch, Peter Ralph Jaeger, William Fitch Kappauf, Melvin Rudin, Norman Francis Kelly, Lawrence Curtis Widdoes, Jr.