Abstract: For synchronisation purposes, a transmitter (TX) multiplexes a pilot carrier with carriers whereon data elements (DATA) are modulated, and transmits the pilot carrier together with the modulated carriers to a receiver (RX). The immunity of the pilot carrier for interferers, such as radio amateur signals, is improved by modulating the pilot carrier with a non-constant signal, for instance a random signal, an alternating signal or even scrambled data elements (DATA), before transmission thereof. Since demodulation of the pilot carrier in the receiver (RX) and averageing successive demodulated pilot carriers reduces the effect of the interference induced on the non-constantly modulated pilot carrier, the degradation of the synchronisation between transmitter (TX) and receiver (RX) is reduced significantly.

Abstract: A Fast Fourier Transform (FFT) dedicated processor includes a scrambler SM scrambling a real input data sequence x(i) and thereby providing two scrambled data subsequences a(i) and b(i). A data generation circuit GC coupled to SM provides a complex data sequence y(i) whose real and imaginary parts equal the scrambled data subsequences a(i) and b(i) respectively. y(i) is applied to an arithmetic unit AU, which under the control of a control unit CoM, is successively converted to an arithmetic means AM, a data regeneration circuit RC and a combinatorial means CM. AM generates an intermediate Fast Fourier Transform series Y(i) of y(i). RC splits up Y(i) into Fast Fourier Transform series A(i) and B(i) of a(i) and b(i) respectively and CM executes a final traditional Fast Fourier Transform combinatorial step and produces the Fast Fourier Transform sequence X(i) of the real input data sequence x(i).

Abstract: The present invention concerns an integrated circuit (1) comprising a standard cell (4), an application cell (2) and a test cell (3) designed in particular to store or to modify from outside the integrated circuit the value of communication signals passing between the standard cell and the application cell. The standard cell executing instructions provided on an instruction bus (3B4) by a program memory located in the application cell in response to an instruction address carried by an instruction address bus (3A4), the conductors of these buses constituting communication links. The integrated circuit further includes a branching circuit for replacing at least one erroneous instruction from the program memory with a replacement instruction previously stored in the integrated circuit in response to a predetermined state of the communication links.

Abstract: A clock signal generator using fractional frequency division is provided comprising a division circuit that produces a clock signal starting from a timing rhythm signal. The frequencies of the two signals are in a division ratio which is the sum of a whole part and a fractional part. A pulse subtractor is provided for receiving the rhythm signal and transmitting it to the division circuit while deleting at least one pulse from this signal upon a command. An accumulator commands a pulse subtractor on each occasion when the product of the number of pulses of the clock signal counted, starting from a time of origin and of the fractional part, changes by unity.

Abstract: A test device for testing integrated electronic chips (EC) includes: a first processor; an interface for interfacing the first processor with a plurality of other circuits; and a second processor coupled to the first processor. In the test device, at least one of the plurality of other circuits is formed on the integrated electronic chip being tested. The interface includes a first scan path having a first string of first cells formed on the integrated electronic chip. The first string of first cells includes a plurality of serially connected first read buffers, a respective one of the first read buffers being provided in each first cell, for latching data and for transferring data between the at least one circuit of the plurality of other circuits and the first processor.