Patents by Inventor Peter Richard Dent
Peter Richard Dent has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230418605Abstract: Disclosed embodiments relate to methods of using a processor to load and duplicate scalar data from a source into a destination register. The data may be duplicated in byte, half word, word or double word parts, according to a duplication pattern.Type: ApplicationFiled: September 7, 2023Publication date: December 28, 2023Inventors: Timothy David Anderson, Duc Quang Bui, Peter Richard Dent
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Publication number: 20230367598Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.Type: ApplicationFiled: March 28, 2023Publication date: November 16, 2023Inventors: Duc Bui, Peter Richard Dent, Timothy D. Anderson
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Patent number: 11755322Abstract: Disclosed embodiments relate to methods of using a processor to load and duplicate scalar data from a source into a destination register. The data may be duplicated in byte, half word, word or double word parts, according to a duplication pattern.Type: GrantFiled: September 24, 2019Date of Patent: September 12, 2023Assignee: Texas Instruments IncorporatedInventors: Timothy David Anderson, Duc Quang Bui, Peter Richard Dent
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Patent number: 11614940Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.Type: GrantFiled: March 29, 2021Date of Patent: March 28, 2023Assignee: Texas Instruments IncorporatedInventors: Duc Bui, Peter Richard Dent, Timothy D. Anderson
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Patent number: 11294826Abstract: A method is provided that includes performing, by a processor in response to a vector permutation instruction, permutation of values stored in lanes of a vector to generate a permuted vector, wherein the permutation is responsive to a control storage location storing permute control input for each lane of the permuted vector, wherein the permute control input corresponding to each lane of the permuted vector indicates a value to be stored in the lane of the permuted vector, wherein the permute control input for at least one lane of the permuted vector indicates a value of a selected lane of the vector is to be stored in the at least one lane, and storing the permuted vector in a storage location indicated by an operand of the vector permutation instruction.Type: GrantFiled: August 26, 2019Date of Patent: April 5, 2022Assignee: Texas Instruments IncorporatedInventors: Timothy David Anderson, Mujibur Rahman, Dheera Balasubramanian Samudrala, Peter Richard Dent, Duc Quang Bui
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Publication number: 20210349832Abstract: A method is provided that includes performing, by a processor in response to a vector permutation instruction, permutation of values stored in lanes of a vector to generate a permuted vector, wherein the permutation is responsive to a control storage location storing permute control input for each lane of the permuted vector, wherein the permute control input corresponding to each lane of the permuted vector indicates a value to be stored in the lane of the permuted vector, wherein the permute control input for at least one lane of the permuted vector indicates a value of a selected lane of the vector is to be stored in the at least one lane, and storing the permuted vector in a storage location indicated by an operand of the vector permutation instruction.Type: ApplicationFiled: July 26, 2021Publication date: November 11, 2021Inventors: Timothy David Anderson, Mujibur Rahman, Dheera Balasubramanian Samudrala, Peter Richard Dent, Duc Quang Bui
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Patent number: 11074193Abstract: A method is provided that includes performing, by a processor in response to a vector permutation instruction, permutation of values stored in lanes of a vector to generate a permuted vector, wherein the permutation is responsive to a control storage location storing permute control input for each lane of the permuted vector, wherein the permute control input corresponding to each lane of the permuted vector indicates a value to be stored in the lane of the permuted vector, wherein the permute control input for at least one lane of the permuted vector indicates a value of a selected lane of the vector is to be stored in the at least one lane, and storing the permuted vector in a storage location indicated by an operand of the vector permutation instruction.Type: GrantFiled: August 26, 2019Date of Patent: July 27, 2021Assignee: Texas Instruments IncorporatedInventors: Timothy David Anderson, Mujibur Rahman, Dheera Balasubramanian Samudrala, Peter Richard Dent, Duc Quang Bui
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Publication number: 20210216313Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.Type: ApplicationFiled: March 29, 2021Publication date: July 15, 2021Inventors: Duc Bui, Peter Richard Dent, Timothy D. Anderson
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Patent number: 10963252Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.Type: GrantFiled: May 24, 2019Date of Patent: March 30, 2021Assignee: Texas Instruments IncorporatedInventors: Duc Bui, Peter Richard Dent, Timothy D. Anderson
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Publication number: 20200371788Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.Type: ApplicationFiled: May 24, 2019Publication date: November 26, 2020Inventors: Duc BUI, Peter Richard DENT, Timothy D. ANDERSON
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Publication number: 20200089495Abstract: Disclosed embodiments relate to methods of using a processor to load and duplicate scalar data from a source into a destination register. The data may be duplicated in byte, half word, word or double word parts, according to a duplication pattern.Type: ApplicationFiled: September 24, 2019Publication date: March 19, 2020Inventors: Timothy David Anderson, Duc Quang Bui, Peter Richard Dent
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Publication number: 20190377690Abstract: A method is provided that includes performing, by a processor in response to a vector permutation instruction, permutation of values stored in lanes of a vector to generate a permuted vector, wherein the permutation is responsive to a control storage location storing permute control input for each lane of the permuted vector, wherein the permute control input corresponding to each lane of the permuted vector indicates a value to be stored in the lane of the permuted vector, wherein the permute control input for at least one lane of the permuted vector indicates a value of a selected lane of the vector is to be stored in the at least one lane, and storing the permuted vector in a storage location indicated by an operand of the vector permutation instruction.Type: ApplicationFiled: August 26, 2019Publication date: December 12, 2019Inventors: Timothy David Anderson, Mujibur Rahman, Dheera Balasubramanian Samudrala, Peter Richard Dent, Duc Quang Bui
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Patent number: 10423413Abstract: A method of loading and duplicating scalar data from a source into a destination register. The data may be duplicated in byte, half word, word or double word parts, according to a duplication pattern.Type: GrantFiled: July 9, 2014Date of Patent: September 24, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Timothy David Anderson, Duc Quang Bui, Peter Richard Dent
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Patent number: 9489197Abstract: This invention is a digital signal processor capable of performing correlation of data with pseudo noise for code division multiple access (CDMA) decoding using clusters. Each cluster includes plural multipliers. The multipliers multiply real and imaginary parts of packed data by corresponding pseudo noise data. Within a cluster the real parts and the imaginary parts of the products are summed separately. This forms plural complex number outputs equal in number to the number of clusters. The pseudo noise data is offset relative to the data input differing amounts for different clusters. The clusters are divided into first half clusters receiving data from even numbered slots and second half clusters receiving data from odd numbered slots. The correlation unit includes a mask input to selectively zero a multiplier product.Type: GrantFiled: July 9, 2014Date of Patent: November 8, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mujibur Rahman, Peter Richard Dent, Timothy David Anderson, Duc Quang Bui
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Publication number: 20150019842Abstract: This invention is a digital signal processor capable of performing correlation of data with pseudo noise for code division multiple access (CDMA) decoding using clusters. Each cluster includes plural multipliers. The multipliers multiply real and imaginary parts of packed data by corresponding pseudo noise data. Within a cluster the real parts and the imaginary parts of the products are summed separately. This forms plural complex number outputs equal in number to the number of clusters. The pseudo noise data is offset relative to the data input differing amounts for different clusters. The clusters are divided into first half clusters receiving data from even numbered slots and second half clusters receiving data from odd numbered slots. The correlation unit includes a mask input to selectively zero a multiplier product.Type: ApplicationFiled: July 9, 2014Publication date: January 15, 2015Inventors: Mujibur Rahman, Peter Richard Dent, Timothy David Anderson, Duc Quang Bui
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Publication number: 20150019838Abstract: A method of loading and duplicating scalar data from a source into a destination register. The data may be duplicated in byte, half word, word or double word parts, according to a duplication pattern.Type: ApplicationFiled: July 9, 2014Publication date: January 15, 2015Inventors: Timothy David Anderson, Duc Quang Bui, Peter Richard Dent
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Patent number: 8880855Abstract: A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that are each addressable by instructions for performing the first and second types of operations. An instruction decode unit is responsive to the at least one multiply instruction of the first type and the at least one multiply instruction of the second type to at the same time enable a first data path between the first set of registers and the first execution unit and to enable a second data path between a second set of registers and the second execution unit.Type: GrantFiled: September 15, 2011Date of Patent: November 4, 2014Assignee: Texas Instruments IncorporatedInventors: Timothy D Anderson, Duc Quang Bui, Eric Biscondi, Shriram D Moharil, Mujibur Rahman, Soujanya Narnur, Peter Richard Dent, Ashish Rai Shrivastava
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Publication number: 20120079247Abstract: A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that are each addressable by instructions for performing the first and second types of operations. An instruction decode unit is responsive to the at least one multiply instruction of the first type and the at least one multiply instruction of the second type to at the same time enable a first data path between the first set of registers and the first execution unit and to enable a second data path between a second set of registers and the second execution unit.Type: ApplicationFiled: September 15, 2011Publication date: March 29, 2012Inventors: Timothy D. Anderson, Duc Quang Bui, Eric Biscondi, Shriram D. Moharil, Mujibur Rahman, Soujanya Narnur, Peter Richard Dent, Ashish Rai Shrivastava
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Patent number: 6108808Abstract: Decoding apparatus for decoding received adaptive differential pulse code modulation data signals which includes unit for quickly detecting errors in the data values in the form of unallocated values or values which are unlikely to occur. The apparatus is intended for use in cordless telephones to eliminate extraneous and disturbing sound signals which can be generated by the decoding apparatus when the signals received by the telephone become weak and are misread before a cyclic redundancy check circuit detects the error.Type: GrantFiled: November 8, 1991Date of Patent: August 22, 2000Assignee: Texas Instruments IncorporatedInventor: Peter Richard Dent