Abstract: A method and an apparatus for generating clock signals is described, by which a period of time can be subdivided into a desired number of essentially equal-length segments. The method and the apparatus are distinguished in that the clock signals are generated based on the outcomes of a repeated subtraction of a first value from a second value. The first value depends on the number of segments into which the period of time to be subdivided is to be subdivided, and the second value depends on the duration of the period of time to be subdivided.

Abstract: The invention relates to a method and an arrangement for operating a bus system having at least one master unit and at least one slave unit, having a bus and a bus control unit for the bus arbitration and for controlling the data transfer. The data transmission is split into a request data transfer and a response data transfer, and, in the time between the request data transfer and the response data transfer, the bus is cleared for the data transmissions of other master units in a first data transmission configuration, or the bus is blocked between the request data transfer and the response data transfer, in a second data transmission configuration and slave units. In the case of a response transfer, the master and slave are changed round.

Abstract: Th present invention relates to a DMA-controller having a definable plurality of transfer channels. According to the present invention such a unit comprises a data processing unit with a bus interface unit being coupled with a bus for transferring data. The data processing unit executes a data transfer on said bus dependent on programmable parameters. It further comprises a parameter memory storing those parameters for each transfer channel, whereby the parameter memory provides a first memory area which stores for each defined transfer channel a word comprising a vector address to a second memory area comprising specific parameters for said transfer channel.

Abstract: A method and a circuit configuration for operation of a bus system. A bus includes a bus control unit which controls only an arbitration and when time is exceeded during a data transmission. An actual data transmission is determined in a respective active master unit and an addressed slave unit. A characteristic of a bus cycle, such as a data length, access to a data area or a control area and a waiting cycle, is transmitted in encoded form through a multiplicity of control lines.

Abstract: A culture bottle assembly for the detection of microorganisms in a fluid sample is provided. The culture bottle assembly is a container having an internal flange which divides the culture bottle into two compartments. A frame having a lower peripheral edge which mates with the internal flange is provided in one compartment. A cap is provided for the container and means are provided for moving the cap axially with respect to the container. A resilient material is provided on the peripheral edge of the cup which is compressed by the cap moving means to provide a liquid tight seal between the two compartments.