Abstract: A job manager may receive a request for a design of a semiconductor device to be verified by a set of computing devices, wherein the request comprises design parameters regarding the design of the semiconductor device. The job manager may provide the design parameters as inputs to a machine learning model trained to predict amounts of computational resources and amounts of compute time for verifying designs of semiconductor devices. The job manager may obtain, as an output from the machine learning model, a predicted amount of computational resources and a predicted amount of compute time for verifying the design of the semiconductor device. The job manager may determine an availability of resources, of the set of computing devices, for verifying the design of the semiconductor device. The job manager may cause the design of the semiconductor device to be verified by one or more computing devices.

Abstract: A system and method is provided for placing gate capacitors, or other performance enhancing electrical components, in an under-utilized standard cell region. The present invention is a layout design tool that allows the designed to automatically intersperse capacitor filler cells around standard cell logic. The present invention includes creating a region, allocated to the particular standard cell, which has (either by intention or situation) low utilization. The design tool of the present invention can also be used to intentionally under-utilize various functional blocks in order to create areas that can be filled with cells containing gate capacitors. The standard cells may or may not be associated with surrounding logic. The place and route filler cells are redefined to include gate capacitors using abutment rules compatible with the standard cells.