Abstract: Methods and apparatus are provided for separating DC and AC components of a composite signal Is=Idc+Iac from a current source, e.g., a photodiode current source. Four current mirrors CM-1 . . . CM-4 are used with common branches and overlap. CM-1 through CM-3 mirror Is and CM-4 mirrors Idc where lac has been removed by a frequency selective branch. Outputs of the Cm-3 and Cm-4 are combined at a node to provide a signal proportional substantially only to Iac. Complementary devices are used where Cm-1 and Cm-4 are of one type and Cm-2 and Cm-3 are of opposite type. The arrangement allows detection of AC signals (e.g., pulses) that are orders of magnitude smaller than the DC background. An I-to-V converter with a large feedback resistance is used at the output to produce a comparatively large voltage output proportional to lac.

Abstract: A rocking-type foot and lower leg exercising apparatus incorporates one or two centrally pivoted pedals mounted upon a base in a position facilitating the placement of the feet of the user upon such pedal or pedals while seated in a chair and rocking of the pedals with the foot positioned upon them to provide a soothing motion that will maintain the tone of the muscles of the legs and encourages blood circulation in the feet and legs. The pivot point of the pedal or pedals may be located at any vertical position between the base and the pedal, but is located longitudinally, between about one fourth to one half of the distance from the end of the pedal or pedals. A motor, solenoid, actuator, or other electrical hydraulic or pneumatic means or any combination thereof may be provided to generate rocking-type motion of the pedals.

Abstract: A rocking-type foot and lower leg exercising apparatus incorporates one or two centrally pivoted pedals mounted upon a base in a position facilitating the placement of the feet of the user upon such pedals while seated in a chair and rocking of the pedals with the foot positioned upon them to provide a soothing motion that will maintain the tone of the muscles of the legs and encourages blood circulation in the feet and legs. The pivot point of the pedals may be located at any vertical position between the base and the pedal, but is located longitudinally between about one fourth to one half of the distance from the end of the heel position on the pedals.

Abstract: A voltage-to-current converter comprises a first MOS transistor for receiving a voltage signal at a first gate and transferring a current signal between a first drain and a first source, a second MOS transistor for receiving a biasing voltage at a second gate and transferring the current signal between a second drain and a second source, and a biasing circuit for applying the biasing voltage of V.sub.C +V.sub.T +kV.sub.DS to the second gate such that the second transistor provides a substantially constant drain-to-source resistance of 1/.beta.V.sub.C, where V.sub.C is a constant voltage, V.sub.T is a threshold voltage for the second transistor, V.sub.DS is a drain-to-source voltage for the second transistor, k is a constant in the range of 1/3 to 2/3, and .beta. is a gain for the second transistor.

Abstract: A modulo 2.sup.2n -1 adder employing adders which may all be standard binary adders. A first binary adder sums binary input signals a and b to produce a first sum signal in which the n+2 more significant bits represent the integer part of (a+b)/2.sup.2n (i.e., of a+b taken modulo 2.sup.2n). A second binary adder subtracts these n+2 more significant bits from a 2n bit shifted (less significant bits) version thereof for producing a first difference signal which is subtracted from the first sum signal in a third binary adder to produce a binary signal R. The signal R is applied to one input of a fourth binary adder which produces the desired modulo 2.sup.2n -1 signal. A comparator circuit applies a constant (2.sup.2n -1) to a difference input of the fourth binary adder only when R is greater than or equal to this constant.

Abstract: A residue to analog converter associated with residue numbers {m1,m2,m3} of the residue number system defined by the moduli set {p1=2.sup.n -1, p2=2.sup.n, p3=2.sup.n +1} and which does not require memory comprises five standard binary adder circuits, apparatus for performing multiplication by bit shifting, and a modulo p1 p3 adder circuit. First and second binary adders combine the residue signals m1 and m3 to produce sum and difference signals which are bit shifted by grounding 2n-1 and n-1 lines, respectively, and locating them as less significant bit lines ahead of these sum and difference signal lines. A modulo p1*p3 adder sums these bit shifted signals. A third binary adder, which ignores overflow, performs a modulo p2=2.sup.n subtraction of m2 from the n less significant bits of the modulo p1*p3 sum signal to produce a second difference signal.

Abstract: In a residue number system defined by the moduli set {p1=2.sup.n -1, p2=2.sup.n, p3=2.sup.n +1}, a method of converting residue numbers {m1,m2,m3} to associated analog signals r(m1,m2,m3) comprises the steps of selecting a first binary signal satisfying the relationships .vertline.m1*S3+m3*S1.vertline..sub.p1*p3 (where the constant S1=p1*p2/2 and S3=p2*p3/2) from a first look-up table; and summing the n less significant bits of this first digital signal and the negative of the residue digit signal m2 in a first binary adder for generating a second binary signal that is representative of the difference therebetween, taken modulo p2. This second binary signal addresses a second look-up table containing third binary signals which correspond to possible values of the product of the second binary signal and p1 and p3. Selected first and third binary signals are summed in a second binary adder for producing a binary output signal r(m1,m2,m3) that is representative of the residue number {m1,m2,m3}.

Abstract: A method is disclosed for accomplishing modulo 2.sup.2n -1 addition with apparatus requiring adders that may be all standard binary adders. The method requires summing binary input signals a and b to produce a first sum signal in which the n+2 more significant bits thereof represent the integer part of a+b taken modulo 2.sup.2n. These n+2 more significant binary bits are subtracted from a 2n bit shifted product representation thereof for producing a first difference signal. This difference signal is subtracted from the first sum signal to produce a binary signal R. When R is greater than or equal to the constant (2.sup.2n -1), this constant is subtracted from the signal R for producing a binary signal that is the first sum signal a+b taken modulo 2.sup.2n -1 .

Abstract: A residue to analog converter associated with residue numbers {m1,m2,m3} of the RNS defined by the moduli set {p1=2.sup.n -1, p2=2.sup.n, p3=2.sup.n +1} comprises a pair of ROMs and a pair of standard binary adders. The first ROM stores a look-up table of summations, taken modulo p1*p2, of possible values of m1*S3 and m3*S1 product terms, where S1=(p1*p2)/2 and S3=(p2*p3)/2, with associated memory locations being addressed by m1 and m3. The first binary adder performs a modulo 2.sup.n summation of a binary signal stored by the first ROM and -m2 by ignoring any overflow. The second ROM stores a look-up table of possible values of the products of p1, p3 and the modulo 2.sup.n signal. The second binary adder sums output signals of the two ROMs for producing a binary signal r(m1,m2,m3) that is representative of the residue signal {m1,m2,m3}. The corresponding analog signal is produced with a standard D/A converter.

Abstract: In a residue number system defined by the moduli set {p1=2.sup.n -1, p2=2.sup.n, p3=2.sup.n +1}, a method of converting residue number signals {m1,m2,m3} to associated analog signals r(m1,m2,m3), and that does not require memory devices, comprises the steps of generating a pair of binary signals that are the sum and difference of the residue numbers m1 and m3, bit shifting these sum and difference signals by inserting 2n-1 and n-1 binary 0's as less significant bits thereof, and summing these bit shifted signals modulo p1*p3 to produce a two dimensional binary signal r(m1,m3). A correction signal is generated by modulo p2=2.sup.n summing the n less significant bits of the signal r(m1,m3 ) and the negative of the residue signal m2 to produce a second difference signal, bit shifting this second difference signal by inserting 2n binary 0's as less significant bits thereof and subtracting the second difference signal from this bit shifted signal to produce the correction signal.