Patents by Inventor Peter S. Bui

Peter S. Bui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6815790
    Abstract: The present invention improves the resolution and accuracy of the presently known two-dimensional position sensing detectors and delivers improved performance in the 1.3 to 1.55 micron wavelength region. The present invention is an array of semiconductor layers with four electrodes, the illustrative embodiment comprising a semi-insulating substrate semiconductor base covered by a semiconductor buffered layer, the buffered layer further covered by a semiconductor absorption layer and the absorption layer covered with a semiconductor layer. Four electrodes are placed on this semiconductor array: two on the top layer parallel to each other and near the ends of opposite edges, and two etched in the buffered layer, parallel to each other and perpendicular to the first set. The layers are doped as to make a p-n junction in the active area. Substantially all the layers, excepting the semi-insulating substrate layer, are uniformly resistive.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: November 9, 2004
    Assignee: Rapiscan, Inc.
    Inventors: Peter S. Bui, Narayan Dass Taneja
  • Publication number: 20040135224
    Abstract: The present invention improves the resolution and accuracy of the presently known two-dimensional position sensing detectors and delivers improved performance in the 1.3 to 1.55 micron wavelength region. The present invention is an array of semiconductor layers with four electrodes, the illustrative embodiment comprising a semi-insulating substrate semiconductor base covered by a semiconductor buffered layer, the buffered layer further covered by a semiconductor absorption layer and the absorption layer covered with a semiconductor layer. Four electrodes are placed on this semiconductor array: two on the top layer parallel to each other and near the ends of opposite edges, and two etched in the buffered layer, parallel to each other and perpendicular to the first set. The layers are doped as to make a p-n junction in the active area. Substantially all the layers, excepting the semi-insulating substrate layer, are uniformly resistive.
    Type: Application
    Filed: January 10, 2003
    Publication date: July 15, 2004
    Inventors: Peter S. Bui, Narayan Dass Taneja