Abstract: An external component of a cochlear implant hearing system. The external component includes a speech processor module operable in a stand-alone mode of operation and a body-worn mode of operation, a protective case configured to have said speech processor module removably mounted therein; and an operational mode controller configured to determine when said speech processor module is mounted in said case and to place said speech processor module in said body-worn mode of operation when said module is mounted in said case.

Abstract: A method for operating an external component of a cochlear implant hearing system. The external component includes a speech processor module operable in a stand-alone mode of operation and a body-worn mode of operation, and a protective case. The method includes operating the speech processor module in the stand-alone mode, determining when the speech processor module is mounted in the case, and operating the speech processor module in the body-worn mode in response to determining that the speech processor module is mounted in the case.

Abstract: An external component of a cochlear implant hearing system. The external component includes a speech processor module operable in a stand-alone mode of operation and a body-worn mode of operation, a protective case configured to have said speech processor module removably mounted therein; and an operational mode controller configured to determine when said speech processor module is mounted in said case and to place said speech processor module in said body-worn mode of operation when said module is mounted in said case.

Abstract: A method for operating an external component of a cochlear implant hearing system. The external component includes a speech processor module operable in a stand-alone mode of operation and a body-worn mode of operation, and a protective case. The method includes operating the speech processor module in the stand-alone mode, determining when the speech processor module is mounted in the case, and operating the speech processor module in the body-worn mode in response to determining that the speech processor module is mounted in the case.

Abstract: Range to a wireless communications node and position relative to one or more wireless communication nodes can be determined with a reduced amount of power consumption. In one example, a probe request is sent at a first power level. Probe responses in response to the probe request are listened for. The number of different radios from which a probe response has been received is counted and compared to a threshold. If the count does not exceed the threshold, then a second different probe request is sent.

Abstract: The location of an item may be determined by first determining a coarse location and then a fine location. In one example, a coarse position of a tagged item is determined using a coarse positioning system and the item's tag. A mobile unit, carrying a fine positioning system, is moved to the determined coarse position. Then, a fine position of the tagged item is determined by communicating between the fine positioning system of the moved mobile unit and the item's tag.

Abstract: A GPS receiver includes baseband resources for simultaneous determination of carrier frequency shift and code chip offset. Reduction in the power consumption of a receiver is achieved by managing the sampling rate of an analog-to-digital converter, the intermediate frequency of the RF front end, and the front end bandwidth so these are appropriate to the current function of the receiver. In a GPS receiver during signal tracking, the IF, front end bandwidth, and ADC sampling rate are set as high as possible; during signal acquisition, the IF and front end bandwidth are set to relatively low values, and the ADC sample rate is set to a high value; and during ephemeris download, the IF, front end bandwidth, and the ADC sample rate are set to relatively low values. When a low battery condition is detected, the IF, front end bandwidth, and the ADC sample rate are set to relatively low values regardless of whether the GPS receiver is in the signal acquisition mode, signal tracking mode, or ephemeris download mode.

Abstract: A sine wave synthesizer is employed in an analog signal processing integrated circuit. The circuit includes an integrator driven from a plurality of integration constant capacitors which are sequentially selected by a clocked decoder. Each capacitor is selected by coupling it between the integrator and a switched reference source. The capacitors are selected so that their sequential selection produces a sine wave approximating current in four increments. A first increment of a sine wave is produced according to an ascending selection of integration constant capacitors. Thereafter, the capacitors are selected in reverse in a descending manner to produce a second increment of the sine wave. The switched capacitor phasing circuit is then operated to invert the sine wave signal to produce the third and fourth increments having a negative instead of a positive excursion. The frequency of the sine wave is controlled by the decoder clock input.

Abstract: A CMOS comparator circuit is disclosed in which a low offset is achieved without trimming. The input stage is composed of a pair of bipolar transistors which have lateral non-dedicated collectors that operate in parallel with the substrate dedicated collectors. The input stage includes matched load devices and is followed by an amplifier having a differential to single ended converter.

Abstract: A CMOS circuit is disclosed for developing a proportional to absolute temperature output current and a temperature invariant semiconductor bandgap voltage.

Abstract: An FSK demodulator is disclosed suitable for use in a CMOS IC using switched capacitor circuits. The mark and space filters are each modified to produce sine and cosine outputs. These outputs are rectified separately and the result summed. The summed outputs are passed through low pass filters and applied to a comparator which determines which of the mark and space signals is dominant. The invention substantially reduces the size of the demodulator filter capacitors and improves the demodulation signal to noise ratio.