Abstract: A fault tolerant multicast ATM switch fabric is constructed as a multistage interconnection network through which cells move from input to output along a pre-established data path. The control phase proceeds concurrently with the data phase by which cells move continuously without idle clock cycles in between. The control logic resolves the state of the switching elements and sends this state information to the data path logic ahead of the cell transfer. The switch consists of three IC designs: control, data path, and switch port controller ICs. The successful realization of the switch relies critically on the design of the control IC which incorporates a new combinatorial hardware design running a dedicated algorithm. A switch port controller delegates, based on local decisions, the replication and routing of multicast cells to a selected group of switch port controllers on a per call basis, thereby supporting any multicast group in a unified manner.