Abstract: The system includes a PIN entry device (PED) for electronic Point of Sale (EPOS) transactions and enhanced security for consumer survey processing. In addition to the usual PED functionality and financial transaction processing, the system allows feedback from a user to be obtained in response to a question. The system displays a text to the user on a display, and prompts a response from the user. The displayed text is determined to be either an approved text (i.e., part of financial transaction) or an unapproved text (i.e., a response to consumer survey). The system and PED are configured to accept responses entered by the user in response to the approved text, and to accept only a single key press response when prompted by a display of the unapproved text, limiting or avoiding a possibility of fraudulently extracting user PIN through consumer survey questions.

Abstract: There is disclosed a PIN entry device (PED) for electronic Point of Sale (EPOS) transactions. In addition to the usual PED functionality, the PED disclosed herein allows feedback from a user to be obtained in response to a question. The PED comprises an alphanumeric display for displaying text to a user, a numeric keypad and one or more function keys. The PED is configured to operate to display text to the user on the alphanumeric display to prompt a response from the user. The displayed text corresponds to approved text and unapproved text. The PED is configured to accept responses entered on the numeric keypad or one or more function keys in response to approved text, and to accept only a single key press response when prompted by a display of unapproved text. A corresponding method is also disclosed.

Abstract: There is disclosed a PIN entry device (PED) for electronic Point of Sale (EPOS) transactions. The PED has enhanced user I/O functionality but retains the strict security and certification framework of such a device. In addition to the usual PED functionality, the PED disclosed herein allows feedback from a user to be obtained in response to a question. The PED comprises an alphanumeric display for displaying text to a user, a numeric keypad and one or more function keys. The PED is configured to operate to display text to the user on the alphanumeric display to prompt a response from the user. The displayed text corresponds to approved text and unapproved text. The PED is configured to accept responses entered on the numeric keypad or one or more function keys in response to approved text, and to accept only a single key press response when prompted by a display of unapproved text. A corresponding method is also disclosed.

Abstract: The present invention provides a system operable to collect customer ratings during a transaction using an electronic point of sale system comprising a computer programmed to effect operation of the electronic point of sale system.

Abstract: A method of collecting, detecting and enumerating microorganisms in a fluid comprising subjecting a sample of the fluid to dielectrophoresis and collecting the microorganisms onto a microelectrode, scanning the microelectrode using a scanning laser and determining the number of microorganisms present on the microelectrode. Alternatively, the microorganisms may be spun onto a substrate which has been pre-treated with a polycationic electrolyte.

Abstract: This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths as narrow as 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is preferably used to fabricate the interconnection circuits. A multi-layer interconnection circuit is fabricated on the glass panel using a release layer. A special assembly layer is formed over the interconnection circuit comprising a thick dielectric layer with openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings using a squeegee to form wells filled with solder. IC chips are provided with gold stud bumps at I/O pad locations, and these bumps are inserted in the wells to form flip chip connections. The IC chips are tested and reworked. The same bump/well connections can be used to attach fine-pitch cables.

Abstract: This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths as narrow as 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is preferably used to fabricate the interconnection circuits. A multi-layer interconnection circuit is fabricated on the glass panel using a release layer. A special assembly layer is formed over the interconnection circuit comprising a thick dielectric layer with openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings using a squeegee to form wells filled with solder. IC chips are provided with gold stud bumps at I/O pad locations, and these bumps are inserted in the wells to form flip chip connections. The IC chips are tested and reworked. The same bump/well connections can be used to attach fine-pitch cables.

Abstract: This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths as narrow as 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is preferably used to fabricate the interconnection circuits. A multi-layer interconnection circuit is fabricated on the glass panel using a release layer. A special assembly layer is formed over the interconnection circuit comprising a thick dielectric layer with openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings using a squeegee to form wells filled with solder. IC chips are provided with gold stud bumps at I/O pad locations, and these bumps are inserted in the wells to form flip chip connections. The IC chips are tested and reworked. The same bump/well connections can be used to attach fine-pitch cables.

Abstract: A method for building scalable electronic subsystems is described. Stackable modules employ copper substrates with solder connections between modules, and a ball grid array interface is provided at the bottom of the stack. A cooling channel is optionally provided between each pair of modules. Each module is re-workable because all integrated circuit attachments within the module employ re-workable flip chip connectors. Also, defective modules can be removed from the stack by directing hot inert gas at externally accessible solder connections.

Abstract: A method for fabricating a copper-based circuit module is described. The module is built on a copper sheet and has isolated feedthroughs fabricated using a glass frit. High density interconnection circuits are built on the copper sheet, including wells for accepting bumped devices such as integrated circuit chips. The modules can be stacked to form electronic subsystems, with cooling channels optionally provided between pairs of modules.

Abstract: A flip chip interface is described between a semiconductor chip and a substrate having interconnection circuits. Flip chip bumps are provided at the active face of the chip; each bump is preferably a flexible copper pillar fabricated on a pad, and terminating at the substrate in a well filled with conductive material. The conductive material may be a conductive powder during testing and rework, converting to a melted solder in the final assembly. A mixed array of pillars is provided: signal pillars for signals and power, and more closely spaced heat pillars for conducting heat away from the chip. The signal pillars may be provided in row and column arrays on a background of heat pillars, and the layout of pillars may be adjusted to match local heat patterns in the chip.

Abstract: A construction for attaching an optical fiber to an electro-optic chip is described. The construction includes support for the optical fiber, optionally provided by an aperture in a supporting copper sheet. High density interconnection circuits are fabricated on the copper sheet. Pillar-in-well connections are used between the electro-optic chip and the interconnection circuits, with electrical connections for signals and power, and thermal connections at increased density for cooling the chip. An electronic subsystem employing stacked modules is described, with optical ports at each of the modules.

Abstract: A test head is described for simultaneous test and/or burn-in of all of the chips on a semiconductor product wafer. The test head is suitable for testing wafers containing high powered chips such as microprocessors. A stimulus wafer is supported on a base with connections for power plus an interface to a test support computer. Attached to a first face of the stimulus wafer are all of the IC chips required to implement test circuits, power distribution, local memory, temperature sensing, and communication interfaces. The second face of the stimulus wafer is used to attach the first face of the product wafer using compliant connectors. The second face of the product wafer is available for cooling. Advanced flip chip connectors are preferably employed for assembling the chips on the stimulus wafer; they enable rework of any chips that prove defective. Embedded in the stimulus wafer are interconnection circuits plus through-wafer connectors. The product wafer is bumped at the I/O pads.

Abstract: An electrostatic energy converter comprising a rotor having a working surface provided with a plurality of distinct charged regions. A stator extends parallel to the rotor and has a working surface facing the working surface of the rotor and being provided with a plurality of spaced-apart electrodes. A power supply is coupled to the electrodes.

Abstract: A test head is described for simultaneous test and/or simultaneous burn-in of all of the chips on a semiconductor wafer, including high powered microprocessor chips. A test execution wafer is attached to a test pedestal with connections for power plus an interface to a test support computer. Mounted on the test execution wafer are all of the IC chips required to implement test circuits, power distribution, local memory, temperature sensing, and communication interfaces. Advanced flip chip connectors are preferably employed for assembling the test execution wafer; they enable rework of any chips that prove defective. Embedded in the test execution wafer are general purpose interconnection circuits plus through-wafer connectors. A test socket employing wells filled with liquid metal is provided on the back side of the test execution wafer. The wafer under test is bumped at the I/O pads, and the bumps are inserted into the wells filled with liquid metal.

Abstract: A tightly packed three-dimensional electronic system or subsystem comprising multiple stacks of semiconductor elements is described. The system is repairable because the elements connect together using re-workable flip chip connectors; each flip chip connector comprises a conductive spring element on one side and a corresponding well filled with solder on the other side. The spring elements relieve stresses at the interfaces and allow the component stacks to remain flat; they also provide vertical compliance for easing assembly of elements that have been imperfectly thinned or planarized. Semiconductor integration platforms may be used to integrate active and passive devices, multi-layer interconnections, through wafer connections, I/O plugs, and terminals for attachment of other semiconductor elements or cables.

Abstract: A method is described for combining the diverse strengths of two materials in a tiled film construction. The first material provides a foundation of intersecting grid lines on a substrate and the second material is contained within the grid lines and has a valued property for a particular application. In a preferred embodiment, a tiled dielectric layer has improved low-k dielectric performance while avoiding film stress problems that can lead to delamination or cracking. CTE mismatch is overcome at the cost of an additional masking step. This tiling method and layered binary construction enable Cytop to be used as a high performance low-k dielectric on most substrates including semiconductor wafers and copper panels or foils.

Abstract: An electronic socket is described for providing either or both temporary and permanent attachments of electronic components to a substrate having interconnection circuits. The socket includes wells filled with a conductive fluid or paste for temporary attachment to the mesas of an electronic circuit. The wells are connected to selected traces of the substrate having interconnection circuits. The temporary connection may be used to produce known good die (KGD), including support of burn-in and high-speed functional test. The mesas can be filled with a material that is hardened after insertion of the mesas for permanent connection of the electronic circuit to the interconnect circuit.

Abstract: A multi-function interface adaptor comprises a base layer and flexible fingers extending from it. The interface adaptor is interposed between two objects to provide a mechanical and/or thermal interface with stress relief or shock absorption. Using bent fingers operating like springs, shocks and distributed stresses can be relieved in the plane of the adaptor, as well as normal to the plane. A preferred embodiment is an Interface Adaptor that replaces thermal grease between a semiconductor chip and its associated heat sink.

Abstract: A Micro Blade is described for implementing an electronic assembly having a thin profile; it is a miniaturized stand-alone unit that is mechanically and thermally rugged, and connects to external components using a cable. The electronic assembly is preferably fabricated on a copper foil substrate including an interconnection circuit, a special assembly layer, and directly attached components. The components are preferably in bare die form, and are preferably attached using plated copper spring elements inserted into wells filled with solder. The copper foil substrate may be folded to form a compact system in package (SEP) inside of the Micro Blade. A jacket comprised of thermally conductive members is formed around the electronic assembly using hermetic seams. The Micro Blade is preferably cooled by immersion in water contained in a tank; the water is cooled and circulated using an external pumping system.