Abstract: Systems and methods for efficient selection of single instruction multiple data operations for neural processing units. An example processor system comprises a matrix processor configured to perform convolutions associated with a neural network and single instruction multiple data (SIMD) processors in communication with the matrix processors, with the SIMD processors being configured to execute a group of operations based on a current position associated with processing the neural network, and with the group of operations being selected from multiple SIMD programs, and with the group of operations being selected from the SIMD programs according to the current position.

Abstract: Systems and methods for enhanced global flags for synchronizing coprocessors. An example processor system includes a plurality of coprocessors configured to compute a processing task, wherein individual coprocessors are connected to individual remaining coprocessors via a plurality of connections, wherein each connection from a coprocessor to a different coprocessor is configured to be asserted, or de-asserted, to indicate a status associated with a global flag of a plurality of global flags, and wherein the global flag is set based on the plurality of coprocessors asserting the global flag.

Abstract: An example matrix processor includes processing elements arranged as a grid, with the matrix processor being configured to receive a first matrix and a second matrix, wherein the first matrix is to be multiplied by the second matrix; transpose the second matrix; organize the second matrix into a plurality of columns, wherein each column is a row of the second matrix; and over one or more cycles, sequentially provide the columns of the second matrix and the rows of the first matrix to the processing elements, wherein the processing elements are configured as multiply-accumulate units (MAC units), and wherein a processing result is stored in the processing elements.

Abstract: Systems and methods for transposing information using shadow latches and active latches for efficient die area in processing system. An example storage includes groups of active latches and shadow latches, with the active/shadow storage receiving a first matrix comprising values, and with the active latches being enabled, over first clock cycles, such that the values are stored in the active latches. The shadow latches replicate the values stored in the active latches. The values replicated in the shadow latches are read over second clock cycles, with at least one value included in a second matrix being stored in at least one active latch over second clock cycles.

Abstract: Systems and methods for enhanced multiply-accumulate units for convolutional neural network processing. An example multiply-accumulate unit includes a multiplier, with the multiplier being configured to receive (1) an input value of a window of input values and (2) a weight value set to negative one. The unit further includes an adder, with the adder being configured to add a result received from the multiplier with a value in an accumulator of the MAC unit. The unit further includes a multiplexer, with the multiplexer being configured to select between outputting (1) a result of the adder and (2) the input value; and the accumulator, and with the accumulator being configured to receive output from the multiplexer, and with the accumulator being configured to be enabled or disabled according to the result of the adder based on the MAC unit performing a particular convolutional operation.

Abstract: Systems and methods for enhanced fractional interpolation for a convolutional processor in autonomous or semi-autonomous systems. An example method includes obtaining images from image sensors positioned about a vehicle. For a first image, an interpolation sequence to interpolate the first image according to a fractional interpolation value is determined, with the interpolation sequence including combinations of respective integer interpolations and integer downsamplings. The first image is interpolated according to the interpolation sequence.

Abstract: Very long instruction word (VLIW) instruction processing using a reduced-width processor is disclosed. In a particular embodiment, a VLIW processor includes a control circuit configured to receive a VLIW packet that includes a first number of instructions and to distribute the instructions to a second number of instruction execution paths. The first number is greater than the second number. The VLIW processor also includes physical registers configured to store results of executing the instructions and a register renaming circuit that is coupled to the control circuit.

Abstract: Very long instruction word (VLIW) instruction processing using a reduced-width processor is disclosed. In a particular embodiment, a VLIW processor includes a control circuit configured to receive a VLIW packet that includes a first number of instructions and to distribute the instructions to a second number of instruction execution paths. The first number is greater than the second number. The VLIW processor also includes physical registers configured to store results of executing the instructions and a register renaming circuit that is coupled to the control circuit.

Abstract: Very long instruction word (VLIW) instruction processing using a reduced-width processor is disclosed. In a particular embodiment, a VLIW processor includes a control circuit configured to receive a VLIW packet that includes a first number of instructions and to distribute the instructions to a second number of instruction execution paths. The first number is greater than the second number. The VLIW processor also includes physical registers configured to store results of executing the instructions and a register renaming circuit that is coupled to the control circuit.

Abstract: Very long instruction word (VLIW) instruction processing using a reduced-width processor is disclosed. In a particular embodiment, a VLIW processor includes a control circuit configured to receive a VLIW packet that includes a first number of instructions and to distribute the instructions to a second number of instruction execution paths. The first number is greater than the second number. The VLIW processor also includes physical registers configured to store results of executing the instructions and a register renaming circuit that is coupled to the control circuit.

Abstract: A system, processor, and method to predict with high accuracy and retain instruction boundaries for previously executed instructions in order to decode variable length instructions is disclosed. In at least one embodiment, a disclosed processor includes an instruction fetch unit, an instruction cache, a boundary byte predictor, and an instruction decoder. In some embodiments, the instruction fetch unit provides an instruction address and the instruction cache produces an instruction tag and instruction cache content corresponding to the instruction address. The instruction decoder, in some embodiments, includes boundary byte logic to determine an instruction boundary in the instruction cache content.

Abstract: A system, processor, and method to predict with high accuracy and retain instruction boundaries for previously executed instructions in order to decode variable length instructions is disclosed. In at least one embodiment, a disclosed processor includes an instruction fetch unit, an instruction cache, a boundary byte predictor, and an instruction decoder. In some embodiments, the instruction fetch unit provides an instruction address and the instruction cache produces an instruction tag and instruction cache content corresponding to the instruction address. The instruction decoder, in some embodiments, includes boundary byte logic to determine an instruction boundary in the instruction cache content.

Abstract: In one embodiment, the present invention includes an apparatus having an instruction selector to select an instruction, where the selector is to store a dependent indicator to indicate a direct dependent consumer instruction of a producer instruction, a decode logic coupled to the instruction selector to receive the dependent indicator when the producer instruction is selected and to generate a wakeup signal for the direct dependent consumer instruction, and wakeup logic to receive the wakeup signal and to indicate that the producer instruction has been selected. Other embodiments are described and claimed.