Abstract: Embodiments provide a scheduler for scheduling test times of a plurality of tester software environments for an automatic test equipment. The scheduler is configured to automatically assign test times to the plurality of tester software environments, to acquire test instructions from a tester software environment of the plurality of tester software environments to which a current test time is assigned, to control the automatic test equipment to perform a test according to the test instructions in order to obtain test results, and to provide the test results to the tester software environment of the plurality of tester software environments to which the current test time is assigned.

Abstract: Embodiments provide a scheduler for scheduling test times of a plurality of tester software environments for an automatic test equipment. The scheduler is configured to automatically assign test times to the plurality of tester software environments, to acquire test instructions from a tester software environment of the plurality of tester software environments to which a current test time is assigned, to control the automatic test equipment to perform a test according to the test instructions in order to obtain test results, and to provide the test results to the tester software environment of the plurality of tester software environments to which the current test time is assigned.

Abstract: A method for testing a digital circuit as a Device under Test—DUT, including determining a Bit Error Rate—BER—value for each one of a determined number of sample points, the BER value representing the ratio of erroneous digital signals to the total number of regarded digital signals, executing a test for each one of the number of sample points by determining whether the determined BER value exceeds a threshold BER value for that sample point, and analyzing the results of executing the test for each one of the number of sample points for providing a statement about the condition of the DUT.

Abstract: Disclosed is a timing generator including a frequency generator for generating an output signal, and circuitry for providing a nominal parameter setting value to the frequency generator for setting a nominal value of a parameter of the output signal, such as frequency, delay time and/or pulse width. The timing generator further includes a memory for storing predefined parameter setting values, whereby the memory is directly coupled to the frequency generator for directly applying parameter setting values stored in the memory to the frequency generator for modifying the nominal value of the parameter.

Abstract: A method for testing a digital circuit as a Device under Test—DUT (110), comprising the steps of determining a Bit Error Rate—BER—value for each one of a determined number of sample points, the BER value representing the ratio of erroneous digital signals to the total number of regarded digital signals, executing a test for each one of the number of sample points by determining whether the determined BER value exceeds a threshold BER value for that sample point, and analyzing the results of the tests of step (b) for providing a statement about the condition of the DUT (110).

Abstract: This invention relates to the operation of common electronic comparators and particularly to an electronic circuit with a comparator for the operational test of integrated circuits (ICs). According to the invention, the electronic circuit comprises a common comparator with an input, an output and a reference input. To the reference input a constant reference voltage is applied. The input voltage to be compared with the reference voltage is superimposed to a time-dependent signal and the resulting voltage is applied to the input of the comparator.

Abstract: A transition time converter for a pulse having steep slopes includes a coil in a series path between an input terminal and an output terminal, as well as a capacitor and a resistor in a shunt path between an input terminal and a reference potential. This transition time converter provides considerably improved reflection characteristics, as compared to prior art transition time converters, while substantially reducing the slopes of the pulses supplied to a load. The coil, capacitor and resistor have values such that the impedance seen by the source looking into the converter is ##EQU1## where R.sub.Z is the output resistance of the source, L is the inductance of the coil and C is the capacitance of the capacitor.

Abstract: A first stripline on a first dielectric carrier material having a first dielectric constant is releasably connected to a second stripline on a second dielectric carrier material having a second dielectric constant by means of an elastic connection strip including a plurality of surface contact strips which extend transversely to its longitudinal direction. In order to reduce reflections at the location of connection, the striplines have the same width and the first carrier material is provided with an additional conductive inner layer, which is connected to ground potential, and, depending on the two dielectric constants and on the thickness of the second carrier material, the distance between the first stripline and the additional conductive inner layer is chosen such that the two striplines have characteristic impedances which correspond to one another.