Abstract: Recurring digital control signals are provided in a predeterminable time frame, with a high time-dependent resolution and flexibility. Data for the control signals are stored in a write/read memory addressed by an address counter. A comparator is clocked with a multiple of the digital signals bit clock, for comparison with the content of a time Table stored in the write/read memory. For convenience in synchronizing to the time frames of adjacent cells in a cellular network, an offset adder may add the complement of a measured offset (delay) to the comparator clock signal, so that it is not necessary to adjust the values stored in the time Table.

Abstract: The divider of the phase locked loop, which control transmitting or receiving frequency, is set to a selected one of a plurality of pre-set values. The selected channel number is entered into one of a bank of registers. The other registers are too short to store the entire binary number corresponding to the lowest division ratio. The lowest division ratio is obtained by concatenating the binary numbers stored in two or more of the registers, and the channel number is then added by binary addition.