Abstract: An integrated circuit includes memory segments, each having at least one memory cell configurable in first and second states to store data, and a controller that controls programming and erasing of the memory segments. The controller maps external memory addresses of write data to internal memory addresses of erased memory segments with no memory cells in the first state such that erased memory segments are programmed with write data. When a write access occurs for an external memory address previously mapped to an internal memory address of a programmed memory segment with at least one memory cell in the first state, the controller remaps the external memory address to another internal memory address of an erased memory segment. The controller identifies programmed memory segments to be erased and controls selective erasure of the identified programmed memory segments, such as programmed memory segments no longer mapped to an external memory address.

Abstract: A determination of the memory state of a resistive n-level memory cell is described. The determination includes charging or discharging a read capacity of the memory cell by applying a voltage between a first electrode and a second electrode of the resistive memory cell. A voltage at the second electrode is compared to a reference voltage to obtain a comparison signal. The comparison signal is sampled at, at least, (n?1) time instants during the charge or discharge of the read capacity to obtain sampling values. The memory state of the memory cell can be determined based upon the sampling values.

Abstract: An integrated circuit includes a plurality of resistivity changing memory cells and at least one resistivity changing reference cell; a voltage comparator including a first and second input terminals; a signal line connected to the memory cells, the reference cell, and the second input terminal; and a switching element connecting the first input terminal to the second input terminal. A method of operating the integrated circuit includes closing the switching element; supplying a first voltage to the first input terminal via the signal line and the switching element; opening the switching element; supplying a second voltage to the second input terminal via the signal line; and comparing the first and second voltages using the voltage comparator, wherein the first voltage represents a memory state of a memory cell, and the second voltage is a reference voltage which represents a memory state of a reference cell, or vice versa.

Abstract: A method and an integrated circuit for determining the state of a resistivity changing memory cell. In one embodiment the method includes detecting a first resistance of the resistivity changing memory cell, determining whether the first resistance value is smaller than a predetermined threshold value thereby determining a first result value, initializing the resistivity changing memory cell into one of at least four resistivity changing memory states, detecting a second resistance value of the resistivity changing memory cell, determining whether the second resistance value is smaller than the predetermined threshold value determining a second result value, and determining the state of the resistivity changing memory cell state using the first and the second result values.

Abstract: A memory includes a first memory device including an array of phase changing memory cells. The first memory device is of a first memory type. The integrated circuit includes a second memory device including an array of phase changing memory cells. The second memory device is of a second memory type that is different than the first memory type. The first and second memory devices are packaged together into a single memory device.

Abstract: An integrated circuit includes memory segments, each having at least one memory cell configurable in first and second states to store data, and a controller that controls programming and erasing of the memory segments. The controller maps external memory addresses of write data to internal memory addresses of erased memory segments with no memory cells in the first state such that erased memory segments are programmed with write data. When a write access occurs for an external memory address previously mapped to an internal memory address of a programmed memory segment with at least one memory cell in the first state, the controller remaps the external memory address to another internal memory address of an erased memory segment. The controller identifies programmed memory segments to be erased and controls selective erasure of the identified programmed memory segments, such as programmed memory segments no longer mapped to an external memory address.

Abstract: A determination of the memory state of a resistive n-level memory cell is described. The determination includes charging or discharging a read capacity of the memory cell by applying a voltage between a first electrode and a second electrode of the resistive memory cell. A voltage at the second electrode is compared to a reference voltage to obtain a comparison signal. The comparison signal is sampled at, at least, (n?1) time instants during the charge or discharge of the read capacity to obtain sampling values. The memory state of the memory cell can be determined based upon the sampling values.

Abstract: The method of operating an integrated circuit including the step of writing to a memory cell, which can assume a first and a second logical state and wherein a change from the second logical state to the first logical state lasts longer than a change from the first logical state to the second logical state, includes reading the logical state of the memory cell, changing, depending on the logical state of the memory cell read, the logical state to the first logical state or retaining the same in the first logical state and, depending on the logical state to be written, changing the logical state to the second logical state or retaining the same in the first logical state.

Abstract: An integrated circuit including a memory with an array of memory cells, each memory cell comprising a non-volatile memory element; and a limited read circuit communicatively coupled to the array of memory cells.

Abstract: A method of operating an integrated circuit is provided. The integrated circuit includes a plurality of resistivity changing memory cells and at least one resistivity changing reference cell; a voltage comparator including a first input terminal and a second input terminal; a signal line being connected to the plurality of resistivity changing memory cells, the at least one resistivity changing reference cell, and the second input terminal; and a switching element connecting the first input terminal to the second input terminal.

Abstract: The method of operating an integrated circuit including the step of writing to a memory cell, which can assume a first and a second logical state and wherein a change from the second logical state to the first logical state lasts longer than a change from the first logical state to the second logical state, includes reading the logical state of the memory cell, changing, depending on the logical state of the memory cell read, the logical state to the first logical state or retaining the same in the first logical state and, depending on the logical state to be written, changing the logical state to the second logical state or retaining the same in the first logical state.

Abstract: An integrated circuit memory device and a method of providing access to multiple memory types within a single integrated circuit memory device are described. In various embodiments, the integrated circuit memory device includes a non-volatile memory array having a first emulated memory region and a second emulated memory region, and a controller having an interface. The memory device is configured to emulate a first emulated memory type and a second emulated memory type. The memory device is further configured to store data in the first emulated memory region when the memory device emulates the first emulated memory type, and in the second emulated memory region when the memory device emulates the second emulated memory type.

Abstract: The invention provides a method for setting and controlling a read latency (L) by means of a FIFO-based read latency control circuit for a read access to a semiconductor memory, having the method steps of providing a common internal clock signal; generating an internal first clock signal and an internal second clock signal, which is different from the first clock signal, from the common clock signal; generating an output pointer for reading out the read data from the first clock signal; generating an input pointer for reading in the read data from the second clock signal; initializing the input and output pointers by allocating a defined, fixedly predetermined time offset between output pointer and input pointer. The invention furthermore provides a corresponding circuit arrangement for carrying out the method.

Abstract: The invention relates to a method for resetting at least one circuit part of an integrated circuit, in particular a synchronous semiconductor memory, in which a clock signal and a clock signal that is inverted with respect to the latter are provided in order to clock the integrated circuit, and in which, when a reset condition is present, an item of reset information is coded onto the clock signal or onto the inverted clock signal. The invention also relates to a circuit arrangement for carrying out the method according to the invention, having a clock suppression device and a decoder circuit, which is intended to extract the reset information from the clock signal or from the inverted clock signal.

Abstract: The invention relates to a method for controlling write access to a semiconductor memory, particularly a DDR graphics memory, in which a multiplicity of data packets are written to the semiconductor memory per data burst, in which write access is initiated by a write command and the data packets which are to be written to the memory are latched under the control of a cycle of a data strobe write clock control signal, where the data packets are latched by alternately using a respective falling and rising edge of the data strobe write clock control signal, and where the data strobe write clock control signal has a defined state at the start of the write operation. The invention also relates to a circuit arrangement for carrying out the method.

Abstract: The invention relates to a parallel-serial converter for converting parallel data into serial data, in particular for or in a DDR semiconductor memory, having at least n input terminals at which n data signals are present in parallel, an output terminal for outputting a serial data signal, a controllable latch connected to the input terminals on the input side, a common storage node, which is connected to outputs of the latch and which holds a data signal of the controllable latch present last, a controllable bypass device, which has an input, which is coupled to the storage node on the output side and which has a control terminal, via which a predeterminable state present at the input of the bypass device can be switched onto the storage node. The invention furthermore relates to a semiconductor memory having such a parallel-serial converter and to a method for operating such a parallel-serial converter.

Abstract: Data transfer is effected on an internal and/or on an external transfer path with or in a semiconductor component, such as a semiconductor memory. A first multiplexer/demultiplexer codes a data sequence by defining a current level and a voltage level for a data signal. The coded sequence is then transferred on the transfer path synchronously with a clock signal and is decoded in a second multiplexer/demultiplexer by evaluation of the received current level and of the received voltage level. From this, the transferred data sequence is determined.

Abstract: An apparatus for generating a second signal having a clock based on a second clock from a first signal with a first clock comprises first and second means for sampling the first signal to determine whether the first signal has a predetermined logic state, wherein first means samples the first signal with the second clock, and second means samples the first signal with a clock phase shifted to the second clock. Means for generating the second signal generates the second signal based on the second clock if it has been determined by at least one means for sampling that the first signal has the predetermined state. Especially for time critical applications, such as a DDR-RAM, a valuable latency saving is provided by the present invention.

Abstract: A Method for initializing an asynchronous latch chain is described, wherein data are taken over through a latch stage at the beginning of the latch chain upon a request signal, the method comprising starting of a clock creation means, like for example a DLL (DLL=delay locket loop), for creating an internal clock on the basis of an external clock, resetting the asynchronous latch chain and applying a start signal to a request signal generation circuit whereupon the creation of a first request signal is enabled on the basis of the internal clock after the clock creation means is settled and after the asynchronous latch chain is reset.

Abstract: A device for driving a memory cell (601) of a memory module which can be operated with an external voltage (VEXT) and an operating frequency (fCLK), whereas the memory cell (601) has a capacitance (600) for storing charges and a transistor (602) for reading charges from the capacitance (600) and for writing charges to the capacitance (600), which transistor can be controlled with a control voltage (VPP), which has a charge store (614) for supplying a control voltage (VPP) which is greater than the external voltage (VEXT). The charge store (614) being able to be charged by the external voltage (VEXT), and the charging of the charge store (614) is able to be controlled by a charging control frequency (fCC) derived from the operating frequency (fCLK) of the memory module.