Patents by Inventor PETER SEALEY

PETER SEALEY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200257646
    Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Applicant: Analog Devices, Inc.
    Inventors: Martin KESSLER, Miguel A. CHAVEZ, Lewis F. LAHR, William HOOPER, Robert Adams, Peter SEALEY
  • Patent number: 10649945
    Abstract: Disclosed herein are systems and techniques for digital interfaces over a two-wire communication bus. For example, an electronic device to interface between a two-wire communication bus and a non-native digital interface may include: a digital interface to support a first digital interface protocol; and a transceiver, coupled to the digital interface, to couple to a link of the two-wire communication bus and to receive data via the link, wherein the data includes commands in accordance with a second digital interface protocol different from the first digital interface protocol; wherein the digital interface is to transmit the commands to a peripheral device in accordance with the second digital interface protocol.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: May 12, 2020
    Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
    Inventors: Philip Gregory Geerling, Eric Zolner, Martin Kessler, Peter Sealey
  • Patent number: 10649948
    Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: May 12, 2020
    Assignee: ANALOG DEVICES, INC.
    Inventors: Martin Kessler, Miguel Chavez, Lewis F. Lahr, William Hooper, Robert Adams, Peter Sealey
  • Publication number: 20190278733
    Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.
    Type: Application
    Filed: May 30, 2019
    Publication date: September 12, 2019
    Applicant: Analog Devices, Inc.
    Inventors: Martin KESSLER, Miguel CHAVEZ, Lewis F. LAHR, William HOOPER, Robert Adams, Peter SEALEY
  • Patent number: 10311010
    Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: June 4, 2019
    Assignee: ANALOG DEVICES, INC.
    Inventors: Martin Kessler, Miguel Chavez, Lewis F. Lahr, William Hooper, Robert Adams, Peter Sealey
  • Publication number: 20160041941
    Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.
    Type: Application
    Filed: October 16, 2015
    Publication date: February 11, 2016
    Applicant: ANALOG DEVICES, INC.
    Inventors: MARTIN KESSLER, MIGUEL CHAVEZ, LEWIS F. LAHR, WILLIAM HOOPER, ROBERT ADAMS, PETER SEALEY