Patents by Inventor PETER SEALEY
PETER SEALEY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11874791Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.Type: GrantFiled: January 31, 2022Date of Patent: January 16, 2024Assignee: Analog Devices, Inc.Inventors: Martin Kessler, Miguel A. Chavez, Lewis F. Lahr, William Hooper, Robert Adams, Peter Sealey
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Publication number: 20230375610Abstract: Systems and techniques for line diagnostics. In particular, disclosed herein are systems and techniques for line diagnostics that sense a state of an electrical cable by using multiple, time-spaced stimuli and detecting their signal reflection time at different threshold levels. Information derived from multiple reflections may be used to determine cable characteristics (e.g., “wire short,” “wire open,” “correctly terminated,” etc.). The systems and techniques disclosed herein may advantageously require less complex hardware and implementation algorithms than conventional time domain reflectometry (TDR) approaches, and thus may be implemented in settings in which TDR was previously unsuitable. Further, if a cable issue is detected, the systems and techniques disclosed herein may determine the approximate location of the cable issue along the cable, accelerating correction of the issue.Type: ApplicationFiled: December 6, 2021Publication date: November 23, 2023Applicant: Analog Devices International Unlimited CompanyInventors: Peter SEALEY, Martin KESSLER, Dan BOYKO, Md Kamruzzaman SHUVO, Matthew PUZEY
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Publication number: 20220156219Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Applicant: Analog Devices, Inc.Inventors: Martin KESSLER, Miguel A. CHAVEZ, Lewis F. LAHR, William HOOPER, Robert Adams, Peter SEALEY
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Patent number: 11238004Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.Type: GrantFiled: April 27, 2020Date of Patent: February 1, 2022Assignee: Analog Devices, Inc.Inventors: Martin Kessler, Miguel A. Chavez, Lewis F. Lahr, William Hooper, Robert Adams, Peter Sealey
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Publication number: 20200257646Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.Type: ApplicationFiled: April 27, 2020Publication date: August 13, 2020Applicant: Analog Devices, Inc.Inventors: Martin KESSLER, Miguel A. CHAVEZ, Lewis F. LAHR, William HOOPER, Robert Adams, Peter SEALEY
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Patent number: 10649945Abstract: Disclosed herein are systems and techniques for digital interfaces over a two-wire communication bus. For example, an electronic device to interface between a two-wire communication bus and a non-native digital interface may include: a digital interface to support a first digital interface protocol; and a transceiver, coupled to the digital interface, to couple to a link of the two-wire communication bus and to receive data via the link, wherein the data includes commands in accordance with a second digital interface protocol different from the first digital interface protocol; wherein the digital interface is to transmit the commands to a peripheral device in accordance with the second digital interface protocol.Type: GrantFiled: December 10, 2018Date of Patent: May 12, 2020Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANYInventors: Philip Gregory Geerling, Eric Zolner, Martin Kessler, Peter Sealey
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Patent number: 10649948Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.Type: GrantFiled: May 30, 2019Date of Patent: May 12, 2020Assignee: ANALOG DEVICES, INC.Inventors: Martin Kessler, Miguel Chavez, Lewis F. Lahr, William Hooper, Robert Adams, Peter Sealey
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Publication number: 20190278733Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.Type: ApplicationFiled: May 30, 2019Publication date: September 12, 2019Applicant: Analog Devices, Inc.Inventors: Martin KESSLER, Miguel CHAVEZ, Lewis F. LAHR, William HOOPER, Robert Adams, Peter SEALEY
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Patent number: 10311010Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.Type: GrantFiled: October 16, 2015Date of Patent: June 4, 2019Assignee: ANALOG DEVICES, INC.Inventors: Martin Kessler, Miguel Chavez, Lewis F. Lahr, William Hooper, Robert Adams, Peter Sealey
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Publication number: 20160041941Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.Type: ApplicationFiled: October 16, 2015Publication date: February 11, 2016Applicant: ANALOG DEVICES, INC.Inventors: MARTIN KESSLER, MIGUEL CHAVEZ, LEWIS F. LAHR, WILLIAM HOOPER, ROBERT ADAMS, PETER SEALEY