Abstract: A method and apparatus for modifying a frequency of an oscillating signal comprises generating an oscillating signal of a predetermined frequency on a semiconductor device used as an evaluation test chip by connecting a predetermine number of circuit elements in a ring oscillator configuration. A delay element operably coupled into the ring oscillator configuration modifies the predetermined frequency of the ring oscillator configuration. The operable coupling may occur on a semiconductor package containing the semiconductor device or a circuit board containing the semiconductor device. A ring oscillator is also described.

Abstract: The use of a compound selected from a range of compounds including quorum sensing molecules, N-acyl homo serine lactones, N-(3-oxododecanoyl)-L-homoserine lactone, inhibitors to modulate STAT activity for the treatment of a range of diseases including cancer, breast cancer, obesity, lipid metabolism disorders, immune disease, immune deficiency or immune disorders. The range of compounds also include compounds of formula (I) in which R is an acyl group of formula (II).

Abstract: A method and structure for external control of an electrostatic discharge (ESD) protection of electronic devices. According to the structure, one or more shunt circuits are coupled to the electronic devices and one or more external contacts are coupled to the one or more shunt circuits. One or more power supplies are further coupled to the one or more shunt circuits prior to the shunt circuits being coupled to the electronic devices. According to the method, the one or more external contacts are operable to be used to perform on or more of: grounding one or more of one or more external contacts coupled to the one or more shunt circuits, supplying one or more DC signals to one or more of the one or more shunt circuits via one or more of the one or more external contacts, and supplying one or more AC signals to one or more of the one or more shunt circuits via one or more of the one or more external contacts.

Abstract: In one aspect, techniques are disclosed for identifying and notifying a circuit designer of signal traces in an integrated circuit design that are closer to each other than a proximity threshold. It is desirable that signal traces be separated from each other by at least the proximity threshold to reduce inter-signal crosstalk to an acceptable level. Such notification may occur either dynamically (while the circuit designer is designing the circuit) or through a report generated after the circuit design has been generated. In another aspect, techniques are disclosed for identifying and notifying the circuit designer of the signal traces that are closest to a reference signal trace. Such notification may provide the circuit designer with feedback about regions in the circuit design which are congested and which may therefore produce an unacceptable level of crosstalk.

Abstract: A signal pathway is presented for routing clock signals from a clock driving device to a circuit component and on to a termination. The signal pathway employs a minimal stub to carry the clock signals to the circuit component without introducing excess signal distortions. A first signal line of the signal pathway is formed on a circuit board and extends from the clock driving device to a first terminal for interfacing with the circuit component. A second signal line of the signal pathway is routed on the circuit component from one end adjacent to and electrically coupled with the first terminal to an opposite end adjacent to and electrically coupled with a second terminal formed on the circuit board. The stub extends from the second signal line on the circuit component. A third signal line of the signal pathway extends on the circuit board from the second terminal to the termination.

Abstract: A method is provided for evaluating trace signal coupling in an electronic design (e.g., a package design). In the method, one or more trace signal coupling rules are formulated. One or more trace pairs designed to carry differential signals are then processed to determine whether the inter-trace spacing between the trace pairs violates the trace signal coupling rules. An indicator (e.g., a DRC and/or a report) is generated to identify violated trace signal coupling rules. Processing of the electronic design may be scoped according one or a group of signal nets, or one or a group of levels of the package design.

Abstract: A method is provided for evaluating via signal coupling in an electronic design (e.g., a package design). In the method, one or more via signal coupling rules are formulated. One or more via pairs designed to carry differential signals are then processed to determine whether the inter-via spacing between the via pairs violates the via signal coupling rules. An indicator (e.g., a DRC and/or a report) is generated to identify violated via signal coupling rules. Processing of the electronic design may be scoped according one or a group of signal nets, or one or a group of levels of the package design.

Abstract: Techniques are disclosed for verifying the proximity of signal return paths (e.g., ground metal or power) to signal traces in an integrated circuit package design. A package designer creates the package design using a package design tool. A proximity verifier verifies that there is a signal return path within a predetermined threshold distance of each specified signal trace in the package layers directly above and/or below the signal trace. The proximity verifier may notify the package designer of any signal traces which are not sufficiently close to signal return paths, such as by providing visual indications of such signal traces in a graphical representation of the package design. In response, the package designer may modify the package model to ensure that all signal traces are sufficiently close to signal return paths.

Abstract: Techniques are disclosed for automatically synthesizing information from a plurality of computer-readable integrated circuit package models. In one embodiment, each of the plurality of package models contains information descriptive of a distinct package. Such information may include, for example, intra-package path lengths and/or propagation delays of signal nets in the modeled packages. Techniques are disclosed for automatically synthesizing such information to produce, for example, aggregate path lengths and/or propagation delays of the signal nets across all of the modeled packages. Such synthesis may be performed even when the package models use mutually inconsistent signal net naming conventions and the modeled packages are composed of different materials. Techniques are also disclosed for providing information to the package designer to assist the package designer in improving the design of the package models.

Abstract: The present invention describes polynucleotides that have been discovered to correlate to the relative intrinsic sensitivity or resistance of cells, e.g., breast cell lines, to treatment with compounds that interact with and modulate, e.g., inhibit, proteintyrosine kinases, such as, for example, members of the Src family of tyrosine kinases, e.g., Src, Fgr, Fyn, Yes, Blk, Hck, Lck and Lyn, as well as other protein tyrosine kinases, including, Bcr-abl, Jak, PDGFR, c-kit and Eph receptors. These polynucleotides have been shown, through a weighted voting cross validation program, to have utility in predicting the resistance and sensitivity of breast cell lines to the compounds. The expression level or phosphorylation status of some polynucleotides is regulated by treatment with a particular protein tyrosine kinase inhibitor compound, thus indicating that these polynucleotides are involved in the protein tyrosine kinase signal transduction pathway, e.g., Src tyrosine kinase.

Abstract: Techniques are disclosed for automatically synthesizing information from a plurality of computer-readable integrated circuit package models. In one embodiment, each of the plurality of package models contains information descriptive of a distinct package. Such information may include, for example, intra-package path lengths and/or propagation delays of signal nets in the modeled packages. Techniques are disclosed for automatically synthesizing such information to produce, for example, aggregate path lengths and/or propagation delays of the signal nets across all of the modeled packages. Such synthesis may be performed even when the package models use mutually inconsistent signal net naming conventions and the modeled packages are composed of different materials. Techniques are also disclosed for providing information to the package designer to assist the package designer in improving the design of the package models.

Abstract: Techniques are disclosed for verifying the proximity of ground vias to signal vias in an integrated circuit package design. A package designer creates the package design using a package design tool. A proximity verifier verifies that there is a ground via within a predetermined threshold distance of each specified signal via in the package design. The proximity verifier may notify the package designer of any signal vias which are not sufficiently close to ground vias, such as by providing visual indications of such signal vias in a graphical representation of the package design displayed on a display monitor. In response, the package designer may modify the package model to ensure that all signal vias are sufficiently close to ground vias. The proximity verifier may be implemented as a design rule which may be executed automatically and in real-time by the package design tool.

Abstract: Techniques are disclosed for verifying the proximity of signal return paths (e.g., ground metal or power) to signal traces in an integrated circuit package design. A package designer creates the package design using a package design tool. A proximity verifier verifies that there is a signal return path within a predetermined threshold distance of each specified signal trace in the package layers directly above and/or below the signal trace. The proximity verifier may notify the package designer of any signal traces which are not sufficiently close to signal return paths, such as by providing visual indications of such signal traces in a graphical representation of the package design. In response, the package designer may modify the package model to ensure that all signal traces are sufficiently close to signal return paths.

Abstract: In one aspect, techniques are disclosed for identifying and notifying a circuit designer of signal traces in an integrated circuit design that are closer to each other than a proximity threshold. It is desirable that signal traces be separated from each other by at least the proximity threshold to reduce inter-signal crosstalk to an acceptable level. Such notification may occur either dynamically (while the circuit designer is designing the circuit) or through a report generated after the circuit design has been generated. In another aspect, techniques are disclosed for identifying and notifying the circuit designer of the signal traces that are closest to a reference signal trace. Such notification may provide the circuit designer with feedback about regions in the circuit design which are congested and which may therefore produce an unacceptable level of crosstalk.

Abstract: An arrangement of an integrated optical waveguide (1) relative to a V-groove (2) for receiving an optical fibre (5) which is to be optically coupled with an end of the waveguide (1) is described. A waveguide (1) is formed in a crystalline optical substrate (3), and a V-groove (2) formed therein beneath an elongate parallel sided window in the substrate with a centre line (2A) of the V-groove (2) aligned with an end (1A) of the waveguide (1). The parallel sides (2B, 2C) of the window at the end of the V-groove (2) aligned with the waveguide (1) terminate out of alignment with each other in a direction along the length of the V-groove whereby the V-groove undercuts a portion (3A) of the optically conducting layer (3) beneath said end of the waveguide (1). The end of the waveguide (1) therefore overhangs the end of the V-groove (2) to enable the end of an optical fibre (5) to be located in close proximity thereto.

Abstract: Techniques are disclosed for automatically synthesizing information from a plurality of computer-readable integrated circuit package models. In one embodiment, each of the plurality of package models contains information descriptive of a distinct package. Such information may include, for example, intra-package path lengths and/or propagation delays of signal nets in the modeled packages. Techniques are disclosed for automatically synthesizing such information to produce, for example, aggregate path lengths and/or propagation delays of the signal nets across all of the modeled packages. Such synthesis may be performed even when the package models use mutually inconsistent signal net naming conventions and the modeled packages are composed of different materials. Techniques are also disclosed for providing information to the package designer to assist the package designer in improving the design of the package models.

Abstract: Lung volume reduction is performed by the placement of a device (2) into a branch of the airway (34) to prevent air from entering that portion of lung. This will result in adsorption atelectasis of the distal portion of lung. The physiological response in this portion of lung is hypoxic vaso-constriction. The net effect is for a portion of lung to be functionally removed, i.e. a selected portion of lung is removed from both the circulation and ventilation. The build up of secretions is accommodated by using a valve (5, 15, 29) in the obstructive device, the valve opening upon coughing etc.

Abstract: Applicant's unique method provides for the use of a single piece of transfer tape for multiple transfers, with the transfer tape being forgiving, clear, having a high shelf life, and being non-self destructive. Such a method has been heretofore unavailable.

Abstract: A method and apparatus for simulating an electronic circuit having a plurality of ports uses a digital processor to identify signal transmission characteristics associated with each of the ports. A plurality of test frequencies are selected with which to measure frequency response of the electronic circuit at each of the ports. For each of the test frequencies, a signal characteristic is identified at each of the ports in response to a sequential application of each of said test frequencies to each port. Scattering parameters corresponding to each port are extracted for each frequency based on the signal characteristics. These scattering parameters are then transformed into a time domain representation of the electronic circuit.

Abstract: A method for holding an end of at least one optic fibre in alignment for optical communication with an end of a respective optic element at a side edge of an optic chip; the method including the steps of: providing a fibre support supporting at least one optic fibre; assembling the fibre support and the optic chip so as to align the end of the at least one optic fibre with the end of the respective optic element at the side edge of the optic chip, wherein the fibre support includes a first portion that is configured to extend beyond the side edge over the optic chip when the end of the at least one optic fibre is aligned with the end of the respective optic element at the side edge; and then bonding said first portion of the fibre support to the optic chip to secure the fibre support to the optic chip.