Abstract: A driver arrangement for a display includes at least one driver, such as a column driver, and a delay line arrangement coupled to the driver. The delay line arrangement delays a data signal provided to the driver by a delay period selectable from a plurality of possible delay periods. The delay line arrangement includes a calibration module that, when requested, is configured and arranged to adjust a current delay period produced by the delay line arrangement towards a predetermined delay period. Displays can include the driver arrangement to provide self-calibration of the delay line.

Abstract: A circuit for pre-emphasis in data serialization. The circuit has a signal delayline to incrementally delay a serialized signal, producing a delayed serialized signal. The circuit has a one bit generator circuit, which determines the interval between receipt of one bit and a second bit. The one bit generator circuit has a strobe delayline to incrementally delay a strobe signal, producing a delayed strobe signal, a logical gate to compare the delayed strobe signal with a second strobe signal, and a logical component to determine how long the delayed strobe signal was delayed before it matched the second strobe signal. The circuit also has a comparison gate to detect transition points in the serialized signal by comparing the delayed serialized signal with the serialized signal. The circuit also has a current source to provide increased current for the serialized signal at the detected transition points.

Abstract: A reconfigurable chip using reconfigurable functional units is modified to better implement linear feedback shift registers. The reconfigurable functional unit has its input multiplexer unit modified so that it can select a combined value. The combined values include some of the bits from the output of the reconfigurable functional unit as well as carry bit from another reconfigurable functional unit. This can significantly reduce the space required to implement linear feedback shift registers which are useful in many digital communication systems.

Abstract: A reconfigurable chip having reconfigurable elements uses an interconnection system which reduces the maximum signal rise and fall time. In one embodiment, the maximum rise and fall time is reduced by providing bypass paths. In another embodiment, buffers are used to reduce signal rise and fall times. Connections between each of the elements are provided by either providing a loop path or by providing bidirectional arrangements of the buffers.

Abstract: A configuration bit layout for a reconfigurable chip includes address bits stored along with configuration bits. The blocks of data are loaded onto the reconfigurable chip from an external memory and the address information is decoded to load the configuration bits onto the correct locations in the reconfigurable chip. In this way, configuration data need not be stored sequentially in the external memory. Configurations can be allocated into different slices of the reconfigurable chip as well.

Abstract: A reconfigurable chip using reconfigurable functional units is modified to better implement linear feedback shift registers. The reconfigurable functional unit has its input multiplexer unit modified so that it can select a combined value. The combined values include some of the bits from the output of the reconfigurable functional unit as well as carry bit from another reconfigurable functional unit. This can significantly reduce the space required to implement linear feedback shift registers which are useful in many digital communication systems.

Abstract: A low voltage differential swing circuit includes a clamping circuit to prevent the output high voltage from exceeding a reference voltage. The low voltage differential swing circuit also includes a current source coupled to a control node and a current steering circuit coupled between the control node and first and second output nodes. The current source provides a constant drive current, and in response to first and second input signals, the current steering circuit generates first and second drive currents, wherein the first and second drive currents together form at the first and second output nodes a differential output signal. The clamping circuit comprises a operational amplifier and a shunting circuit. The operational amplifier senses the difference between a reference voltage and a voltage level at the control node, which voltage level varies in relation to the voltage level of the differential output signal.