Abstract: In accordance with one aspect the present disclosure is directed toward a method for detecting arc faults on a power line. The method may include monitoring power signals associated with a power line and filtering the power signals to produce a high frequency signal and a low frequency signal. A mask signal may generated based on the low frequency signal, and the high frequency signal may be analyzed to extract a broadband portion of the high frequency signal. A fault counter may be incremented if the magnitude of the broadband portion is approximately greater than a first threshold level. A fault counter may be decremented if the magnitude of the broadband portion is approximately less than the first threshold level. A trip signal is provided to a switching device associated with the power line if the fault counter exceeds a predetermined fault limit.

Abstract: In accordance with one aspect the present disclosure is directed toward a method for detecting arc faults on a power line. The method may include monitoring power signals associated with a power line and filtering the power signals to produce a high frequency signal and a low frequency signal. A mask signal may generated based on the low frequency signal, and the high frequency signal may be analyzed to extract a broadband portion of the high frequency signal. A fault counter may be incremented if the magnitude of the broadband portion is approximately greater than a first threshold level. A fault counter may be decremented if the magnitude of the broadband portion is approximately less than the first threshold level. A trip signal is provided to a switching device associated with the power line if the fault counter exceeds a predetermined fault limit.

Abstract: Certain exemplary embodiments can comprise an arc fault detection circuit. The arc fault detection circuit can comprise a zero crossing analysis sub-system comprising a counter configured to determine, for a first waveform, a count of dips that occur between a pair of predetermined zero crossings of a second waveform. The second waveform can be obtained from an electrical circuit.

Abstract: A feedback coder, which employs simple CMOS push/pull amplifiers as gain elements, along with a bistable circuit, in its preferred embodiment takes the form of a second-order delta-sigma modulator. The output of the modulator is converted into pulse code modulated words by a finite impluse response filter which incorporates a partial coefficient generator utilizing simplified logic. The generator output is provided to an accumulator in which the stage operate at reduced speed. A simple multiplexer generates a serial output. The entire converter can be integrated on a semiconductor chip of relatively small area.

Abstract: A feedback coder, which employs simple CMOS push/pull amplifiers as gain elements, along with a bistable circuit, in its preferred embodiment takes the form of a second-order delta-sigma modulator. The output of the modulator is converted into pulse code modulated words by a finite impulse response filter which incorporates a partial coefficient generator utilizing simplified logic. The generator output is provided to an accumulator in which the stages operate at reduced speed. A simple multiplexer generates a serial output. The entire converter can be integrated on a semiconductor chip of relatively small area.

Abstract: A feedback coder, which employs simple CMOS push/pull amplifiers as gain elements, along with a bistable circuit, in its preferred embodiment takes the form of a second-order delta-sigma modulator. The output of the modulator is converted into pulse code modulated words by a finite impulse response filter which incorporates a partial coefficient generator utilizing simplified logic. The generator output is provided to an accumulator in which the stages operate at reduced speed. A simple multiplexer generates a serial output. The entire converter can be integrated on a semiconductor chip of relatively small area.

Abstract: The input digital signal is applied to a transition detector which causes an up/down counter to increment or decrement each time a transition is detected. The output of the counter is utilized to address a read only memory (ROM) which, in turn, generates binary words representing first and second integers. These binary words are used to control a programmable divider to generate an output having a frequency which moves between two values corresponding to the digital input. The rate at which the frequency changes between the two values is controlled by the ROM contents. In the implementation, the frequency changes with a raised cosine shape.