Abstract: In some examples, this disclosure describes a method of controlling a high-side power switch and a low-side power switch arranged in a half bridge configuration. The method may comprise driving the gate of the high-side power switch based on high-side pulse modulation (PM) signals; driving a gate of the low-side power switch based on low-side PM signals; and monitoring the high-side PM signals and the low-side PM signals. The high-side PM signals and the low-side PM signals are configured to turn the high-side power switch and the low-side power switch ON and OFF in a complementary fashion, and monitoring may include: detecting one or more absences of either the high-side PM signals or the low-side PM signals; and generating a fault signal in response to detecting the one or more absences.

Abstract: A driver circuit controls a half-bridge that includes a high-side power switch and a low-side power switch. The driver circuit may comprise a high-side compare unit configured to determine a first drain-to-source voltage, wherein the first drain-to-source voltage is associated with the high-side power switch when the high-side power switch is ON, and a low-side compare unit configured to determine a second drain-to-source voltage, wherein the second drain-to-source voltage is associated with the low-side power switch when the low-side power switch is ON. The high-side compare unit may be further configured to determine a third drain-to-source voltage, wherein the third drain-to-source voltage is associated with the high-side power switch when the high-side power switch is OFF, and the low-side compare unit may be further configured to determine a fourth drain-to-source voltage, wherein the fourth drain-to-source voltage is associated with the low-side power switch when the low-side power switch is OFF.

Abstract: A driver circuit controls a half-bridge that includes a high-side power switch and a low-side power switch. The driver circuit may comprise a high-side compare unit configured to determine a first drain-to-source voltage, wherein the first drain-to-source voltage is associated with the high-side power switch when the high-side power switch is ON, and a low-side compare unit configured to determine a second drain-to-source voltage, wherein the second drain-to-source voltage is associated with the low-side power switch when the low-side power switch is ON. The high-side compare unit may be further configured to determine a third drain-to-source voltage, wherein the third drain-to-source voltage is associated with the high-side power switch when the high-side power switch is OFF, and the low-side compare unit may be further configured to determine a fourth drain-to-source voltage, wherein the fourth drain-to-source voltage is associated with the low-side power switch when the low-side power switch is OFF.

Abstract: A driver circuit may be configured to control a power switch. The driver circuit may comprise an output pin configured to deliver signals to a gate of the power switch to control an ON/OFF state of the power switch, and a comparator configured to compare a gate-to-source voltage of the power switch to a first threshold when the power switch is ON and to compare the gate-to-source voltage of the power switch to a second threshold when the power switch is OFF.