Patents by Inventor Peter Stewart Colyer

Peter Stewart Colyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Test mode matrix circuit for an embedded microprocessor core
    Patent number: 5954824
    Abstract: A test mode matrix circuit in an integrated circuit switches signal lines internal to the integrated circuit in a manner that allows an embedded microprocessor within the integrated circuit to be fully functionally tested using standard test vectors applied to the integrated circuit, and which allows for debugging the code written for an embedded microprocessor core by connecting an in-circuit emulator (ICE) to the integrated circuit. The test mode matrix circuit operates in a number of mutually exclusive modes, each of which is suitably selected via control signal inputs to the test mode matrix. The test mode matrix circuit couples signals from the embedded microprocessor to the application-specific logic without passing through off-chip drivers/receivers. Multiple microprocessors and corresponding test mode matrices may also be implemented on the same integrated circuit.
    Type: Grant
    Filed: September 11, 1997
    Date of Patent: September 21, 1999
    Assignee: International Business Machines Corporation
    Inventors: Cory Ansel Cherichetti, Peter Stewart Colyer, David Robert Stauffer
  • Test mode matrix circuit for an embedded microprocessor core
    Patent number: 5724502
    Abstract: A test mode matrix circuit in an integrated circuit switches signal lines internal to the integrated circuit in a manner that allows an embedded microprocessor within the integrated circuit to be fully functionally tested using standard test vectors applied to the integrated circuit, and which allows for debugging the code written for an embedded microprocessor core by connecting an in-circuit emulator (ICE) to the integrated circuit. The test mode matrix circuit operates in a number of mutually exclusive modes, each of which is suitably selected via control signal inputs to the test mode matrix. The test mode matrix circuit couples signals from the embedded microprocessor to the application-specific logic without passing through off-chip drivers/receivers. Multiple microprocessors and corresponding test mode matrices may also be implemented on the same integrated circuit.
    Type: Grant
    Filed: August 7, 1995
    Date of Patent: March 3, 1998
    Assignee: International Business Machines Corporation
    Inventors: Cory Ansel Cherichetti, Peter Stewart Colyer, David Robert Stauffer