Abstract: A method heteroepitaxially deposits a silicon germanium layer on a substrate. The silicon germanium layer has a composition Si1-xGex, where 0.01?x?1. The substrate is a silicon single crystal wafer or a silicon-on-insulator wafer. The method includes: providing a mask layer atop the substrate; removing the mask layer in an edge region of the substrate to provide access to an annular-shaped free surface of the substrate in the edge region of the substrate surrounding a remainder of the mask layer; depositing an edge reservoir consisting of a relaxed or partially relaxed silicon germanium layer atop the annular-shaped free surface of the substrate; removing the remainder of the mask layer; and depositing the silicon germanium layer atop the substrate and atop the edge reservoir, the silicon germanium layer contacting an inner lateral surface of the edge reservoir.

Abstract: Suitability of silicon wafers for use in device processing without generation of fatal defects is assessed by using SIRD to measure stress in a wafer cut from a piece of a crystal ingot after first and second thermal treatments of the water, the second thermal treatment consisting of a heating phase, a holding phase, and a cooling phase. The result is used to consider whether silicon wafers cut from the piece can adequately survive device processing without generating excess defects.

Abstract: A layered semiconductor substrate has a monocrystalline first layer based on silicon, having a first thickness and a first lattice constant a1 determined by a first dopant element and a first dopant concentration, and in direct contact therewith, a monocrystalline second layer based on silicon, having a second thickness and a second lattice constant a2, determined by a second dopant element and a second dopant concentration, and a monocrystalline third layer comprising a group III nitride, the second layer located between the first layer and the third layer, wherein a2>a1, wherein the crystal lattice of the first layer and the second layer are lattice-matched, and wherein the bow of the layered semiconductor substrate is in the range from ?50 ?m to 50 ?m.

Abstract: A semiconductor wafer has a silicon single crystal substrate having a top surface and a stack of layers covering the top surface, the stack of layers containing an AlN nucleation layer covering the top surface of the silicon single crystal substrate, wherein the top surface of the silicon single crystal substrate has a crystal lattice orientation which is off-oriented with respect to the {111}-plane, the normal to the top surface being inclined with respect to the <111>-direction toward the <11-2>-direction by an angle ? of not less than 0.3° and not more than 6°, the azimuthal tolerance of the inclination being ±0.1°; and an AlGaN buffer layer which covers the AlN nucleation layer and contains one or more AlxGa1-xN layers, wherein 0<×<1.

Abstract: An epitaxial wafer comprises a silicon substrate wafer having first and second sides, and a silicon epitaxial layer deposited on the first side, and optionally one or more additional epitaxial layers on top of the silicon epitaxial layer, at least one of the silicon epitaxial layer or at least one of the one or more additional epitaxial layers being doped with nitrogen at a concentration of 1×1016 atoms/cm3 or more and 1×1020 atoms/cm3 or less. The epitaxial wafer is produced by depositing the silicon epitaxial layer and/or at least one of the one or more additional epitaxial layers, at a deposition temperature of 940° C. or less through chemical vapor deposition in the presence of a deposition gas atmosphere containing one or more silicon precursor compounds and one or more nitrogen precursor compounds.

Abstract: A semiconductor wafer has a silicon single crystal substrate having a top surface and a stack of layers covering the top surface, the stack of layers containing an AlN nucleation layer covering the top surface of the silicon single crystal substrate, wherein the top surface of the silicon single crystal substrate has a crystal lattice orientation which is off-oriented with respect to the {111}-plane, the normal to the top surface being inclined with respect to the <111>-direction toward the <11-2>-direction by an angle ? of not less than 0.3° and not more than 6°, the azimuthal tolerance of the inclination being ±0.1°; and an AlGaN buffer layer which covers the AlN nucleation layer and contains one or more AlxGa1-xN layers, wherein 0<x<1.

Abstract: An epitaxial wafer comprises a silicon substrate wafer having first and second sides, and a silicon epitaxial layer deposited on the first side, and optionally one or more additional epitaxial layers on top of the silicon epitaxial layer, at least one of the silicon epitaxial layer or at least one of the one or more additional epitaxial layers being doped with nitrogen at a concentration of 1×1016 atoms/cm3 or more and 1×1020 atoms/cm3 or less. The epitaxial wafer is produced by depositing the silicon epitaxial layer and/or at least one of the one or more additional epitaxial layers, at a deposition temperature of 940° C. or less through chemical vapor deposition in the presence of a deposition gas atmosphere containing one or more silicon precursor compounds and one or more nitrogen precursor compounds.

Abstract: A layered semiconductor substrate has a monocrystalline first layer based on silicon, having a first thickness and a first lattice constant a1 determined by a first dopant element and a first dopant concentration, and in direct contact therewith, a monocrystalline second layer based on silicon, having a second thickness and a second lattice constant a2, determined by a second dopant element and a second dopant concentration, and a monocrystalline third layer comprising a group III nitride, the second layer located between the first layer and the third layer, wherein a2>a1, wherein the crystal lattice of the first layer and the second layer are lattice-matched, and wherein the bow of the layered semiconductor substrate is in the range from ?50 ?m to 50 ?m.

Abstract: SOI wafers are manufactured by forming on a silicon substrate a monocrystalline first, cubic 1a-3 metal or mixed metal oxide layer whose lattice constant differs from that of the substrate by 5% or less; forming a second cubic 1a-3 mixed metal oxide layer having a lattice constant within 2% of the lattice constant of the first metal or mixed metal oxide layer, and having a graded metal content to vary the lattice content in the second mixed metal oxide layer from that of the first layer, and thermally treating the layered product in an oxygen atmosphere to form an amorphous interlayer between the substrate and the first metal or mixed metal oxide layer.

Abstract: A multilayer semiconductor wafer has a substrate wafer having a first side and a second side; a fully or partially relaxed heteroepitaxial layer deposited on the first side of the substrate wafer; and a stress compensating layer deposited on the second side of the substrate wafer. The multilayer semiconductor wafer is produced by a method including depositing on a first side of a substrate a fully or partially relaxed heteroepitaxial layer at a deposition temperature; and at the same temperature or before significantly cooling the wafer from the deposition temperature, providing a stress compensating layer on a second side of the substrate.

Abstract: A method for producing a wafer with a silicon single crystal substrate having a front and a back side and a layer of SiGe deposited on the front side, the method using steps in the following order: simultaneously polishing the front and the back side of the silicon single crystal substrate; depositing a stress compensating layer on the back side of the silicon single crystal substrate; polishing the front side of the silicon single crystal substrate; cleaning the silicon single crystal substrate having the stress compensating layer deposited on the back side; and depositing a fully or partially relaxed layer of SiGe on the front side of the silicon single crystal substrate.

Abstract: A method for producing a wafer with a silicon single crystal substrate having a front and a back side and a layer of SiGe deposited on the front side, the method using steps in the following order: simultaneously polishing the front and the back side of the silicon single crystal substrate; depositing a stress compensating layer on the back side of the silicon single crystal substrate; polishing the front side of the silicon single crystal substrate; cleaning the silicon single crystal substrate having the stress compensating layer deposited on the back side; and depositing a fully or partially relaxed layer of SiGe on the front side of the silicon single crystal substrate.

Abstract: A layered semiconductor wafer contains the following layers in the given order: a monocrystalline substrate wafer (1) containing substantially silicon, a first amorphous intermediate layer (2) of an electrically insulating material having a thickness of 2 nm to 100 nm, a monocrystalline first oxide layer (3) having a cubic Ia-3 crystal structure, a composition of (M12O3)1-x(M22O3)x wherein each of M1 and M2 is a metal and wherein 0?x?1, and a lattice constant which differs from the lattice constant of the material of the substrate wafer by 0% to 5%. The invention also relates to a process for manufacturing such semiconductor wafers by epitaxial deposition.

Abstract: A layered semiconductor wafer contains the following layers in the given order: a monocrystalline substrate wafer (1) containing substantially silicon, a first amorphous intermediate layer (2) of an electrically insulating material having a thickness of 2 nm to 100 nm, a monocrystalline first oxide layer (3) having a cubic Ia-3 crystal structure, a composition of (M12O3)1-x(M22O3)x wherein each of M1 and M2 is a metal and wherein 0?x?1, and a lattice constant which differs from the lattice constant of the material of the substrate wafer by 0% to 5%. The invention also relates to a process for manufacturing such semiconductor wafers by epitaxial deposition.

Abstract: A multilayer structure, comprises a substrate and a layer of silicon and germanium (SiGe layer) deposited heteroepitaxially thereon having the composition Si1-xGex and having a lattice constant which differs from the lattice constant of silicon, and a thin interfacial layer deposited on the SiGe layer and having the composition Si1-yGey, which thin interfacial layer binds threading dislocations, and at least one further layer deposited on the interfacial layer.

Abstract: A multilayer structure, comprises a substrate and a layer of silicon and germanium (SiGe layer) deposited heteroepitaxially thereon having the composition Si1-xGex and having a lattice constant which differs from the lattice constant of silicon, and a thin interfacial layer deposited on the SiGe layer and having the composition Si1-yGey, which thin interfacial layer binds threading dislocations, and at least one further layer deposited on the interfacial layer.

Abstract: A multilayer semiconductor wafer has a substrate wafer having a first side and a second side; a fully or partially relaxed heteroepitaxial layer deposited on the first side of the substrate wafer; and a stress compensating layer deposited on the second side of the substrate wafer. The multilayer semiconductor wafer is produced by a method including depositing on a first side of a substrate a fully or partially relaxed heteroepitaxial layer at a deposition temperature; and at the same temperature or before significantly cooling the wafer from the deposition temperature, providing a stress compensating layer on a second side of the substrate.

Abstract: A multilayer semiconductor wafer has a substrate wafer having a first side and a second side; a fully or partially relaxed heteroepitaxial layer deposited on the first side of the substrate wafer; and a stress compensating layer deposited on the second side of the substrate wafer. The multilayer semiconductor wafer is produced by a method including depositing on a first side of a substrate a fully or partially relaxed heteroepitaxial layer at a deposition temperature; and at the same temperature or before significantly cooling the wafer from the deposition temperature, providing a stress compensating layer on a second side of the substrate.

Abstract: A layered semiconductor wafer contains the following layers in the given order: a monocrystalline substrate wafer (1) containing substantially silicon, a first amorphous intermediate layer (2) of an electrically insulating material having a thickness of 2 nm to 100 nm, a monocrystalline first oxide layer (3) having a cubic Ia-3 crystal structure, a composition of (M12O3)1-x(M22O3)x wherein each of M1 and M2 is a metal and wherein 0?x?1, and a lattice constant which differs from the lattice constant of the material of the substrate wafer by 0% to 5%. The invention also relates to a process for manufacturing such semiconductor wafers by epitaxial deposition.

Abstract: A multilayer structure, comprises a substrate and a layer of silicon and germanium (SiGe layer) deposited heteroepitaxially thereon having the composition Si1-xGex and having a lattice constant which differs from the lattice constant of silicon, and a thin interfacial layer deposited on the SiGe layer and having the composition Si1-yGey, which thin interfacial layer binds threading dislocations, and at least one further layer deposited on the interfacial layer.