Abstract: A phase control thyristor includes a main gate structure and a plurality of local emitter shorts dots arranged in a shorts pattern on a cathode side of the thyristor. The main gate structure includes longitudinal main gate beams extending from a center region of the cathode side towards a circumferential region. Neighboring main gate beams are arranged with a distance with respect to an associated intermediate middle line. The shorts pattern is more homogeneous in a region closer to a main gate beam than in a region closer to an associated middle line. Adaptions to match shorts patterns in neighboring segments of the cathode side surface are made in regions away from the main gate beams such that an electron hole plasma spreading from the main gate beam is not interfered by any inhomogeneity of the shorts dots pattern. The design rules enable an improvement of the thyristor operational characteristics.

Abstract: The power semiconductor device with a four-layer npnp structure can be turned-off via a gate electrode. The first base layer comprises a cathode base region adjacent to the cathode region and a gate base region adjacent to the gate electrode, but disposed at a distance from the cathode region. The gate base region has the same nominal doping density as the cathode base region in at least one first depth, the first depth being given as a perpendicular distance from the side of the cathode region, which is opposite the cathode metallization. The gate base region has a higher doping density than the cathode base region and/or the gate base region has a greater depth than the cathode base region in order to modulate the field in blocking state and to defocus generated holes from the cathode when driven into dynamic avalanche.

Abstract: The power semiconductor device with a four-layer npnp structure can be turned-off via a gate electrode. The first base layer comprises a cathode base region adjacent to the cathode region and a gate base region adjacent to the gate electrode, but disposed at a distance from the cathode region. The gate base region has the same nominal doping density as the cathode base region in at least one first depth, the first depth being given as a perpendicular distance from the side of the cathode region, which is opposite the cathode metallization. The gate base region has a higher doping density than the cathode base region and/or the gate base region has a greater depth than the cathode base region in order to modulate the field in blocking state and to defocus generated holes from the cathode when driven into dynamic avalanche.

Abstract: The presented invention relates to monoclonal antibodies useful in sensitive and specific immunological assays for the identification of prions in various tissues and body fluids, the production of such monoclonal antibodies by means of immunization of PrP0/0 mice by means of a new recombinant fragment of PrP and the use of the antibodies, e.g. for therapeutic and preventive treatments of humans and animals suffering from prion diseases.

Abstract: The presented invention relates to monoclonal antibodies useful in sensitive and specific immunological assays for the identification of prions in various tissues and body fluids, the production of such monoclonal antibodies by means of immunization of PrP0/0 mice by means of a new recombinant fragment of PrP and the use of the antibodies, e.g. for therapeutic and preventive treatments of humans and animals suffering from prion diseases.

Abstract: The integrated gate dual transistor (IGDT) has two controllable gates (G1, G2), a first gate (G1) being provided on the cathode side and being driven via a low-inductance first gate terminal with a first gate current, and a second gate (G2) being provided on the anode side and being driven via a low-inductance second gate terminal with a second gate current. In the switch-off operation of the IGDT, the rate of rise of the voltage across the IGDT is limited via the two gates. Limiting the rate of rise of the voltage across the IGDT prevents voltages from building up at different speeds in a series circuit of IGDTs, and thus unequal loads from overheating and destroying the individual IGDTs.

Abstract: The power semiconductor device has a pn junction between two power electrodes (2, 3). A control electrode (4) is arranged in the region of one of the two power electrodes (3). A current can be fed in via the control electrode, which current can be used to raise the current through the power electrodes. As a result, the reverse current can be raised in the blocking state of the device.

Abstract: The integrated gate dual transistor (IGDT) has two controllable gates (G1, G2), a first gate (G1) being provided on the cathode side and being driven via a low-inductance first gate terminal with a first gate current, and a second gate (G2) being provided on the anode side and being driven via a low-inductance second gate terminal with a second gate current. In the switch-off operation of the IGDT, the rate of rise of the voltage across the IGDT is limited via the two gates.

Abstract: A turn-off high power semiconductor device with the inner pnpn-layer structure of a Gate-Commutated Thyristor and a first gate on the cathode side has an additional second gate on the anode side, said second gate contacting the n-doped base layer and having a second gate contact. A second gate lead which is of rotationally symmetrical design and is disposed concentrically with respect to the anode contact is in contact with said second gate contact. Said second gate lead is brought out of the component and electrically insulated from the anode contact.

Abstract: A specification is given of a bidirectionally controllable thyristor which is distinguished by improved decoupling between the two thyristor structures. In particular, the intention is that the switched-off structure cannot be triggered in an uncontrolled manner by undesirable migration of charge carriers. This is achieved by virtue of the fact that the degree of shorting of the cathode region increases toward the isolation region. In particular, this can be achieved by virtue of the fact that the density per unit area of the short-circuit regions tends to a maximum value toward the isolation region. The use of a linear, continuous short-circuit region running along the isolation region is particularly favorable. (FIG. 1).

Abstract: A thyristor according to the invention comprises a layer sequence containing an n-type emitter layer (4), a p-type base layer (5), an n-type base layer (6) and a p-type emitter layer (7) in a semiconductor substrate (3) between an anode (1) and a cathode (2). The p-type emitter layer (7) is perforated by anode short-circuit zones (8) and is thereby subdivided into sections. In this arrangement, the anode short circuits (8) short-circuit the n-type base layer (6) to the anode (1). Disposed between the anode short circuits (8) and the p-type emitter layer (7) is a p-type barrier layer (9), also referred to as p-type soft layer. According to the invention, said p-type barrier layer (9) has gaps (12) in which the n-type base (6) is contacted by the anode (1) either directly or via an anode short circuit (8).

Abstract: To provide thermal relief, particularly of the edge of disk-shaped gate-turn-off GTO thyristors (GTO) as are used in converters in power electronics, at least one cooling segment which is isolated from a GTO cathode metallization of the GTO thyristor segment (GTO) by a gate electrode metallization of a gate electrode is arranged on the edge and laterally adjacent to the GTO thyristor segment (GTO). An insulation layer is provided between a cooling segment metallization and the gate electrode metallization. Cooling segments in an lo outer annular zone can be alternately arranged with GTO thyristor segments (GTO) or offset towards the outside in the radial direction or perpendicular direction thereto. Instead of cooling segments, a p.sup.+ -type GTO emitter layer of the GTO thyristor segments (GTO) can be shortened at the edge in the outer annular zone.

Abstract: A GTO having a cathode emitter (7) is specified, which cathode emitter has a low emission efficiency. This cathode emitter (7) provides a clearly increased resistance to the formation of current filaments. As a result, relatively high turn-off current densities can be reliably mastered. In addition, the fraction of the hole current in the total current is more than 10%. This is achieved, for example, by selecting the penetration depth as <1 .mu.m and the edge concentration as <10.sup.19 cm.sup.-3.

Abstract: A liquid crystal display device having two linear polarisers and a nematic liquid crystal with positive dielectric anisotropy. The liquid crystal is illuminated by a light source which is arranged in a fixed spatial relationship to the display. Behind the display, a diffusely scattering, metallic reflector is provided. The angle of incidence of the light relative to the perpendicular on the surface of the front carrier plate is in the range from 50.degree. to 90.degree., preferably between 70.degree. and 80.degree.. The operating voltage of the display device according to the invention is less than 2.0 times the Freedericksz threshold voltage of the liquid crystal. In this way, optimum contrast is achieved, coupled with a very large range of viewing angle. With this display device, very high multiplex rates (up to 1:120) can be reached.

Abstract: An electric contact arrangement for liquid crystal display cells is disclosed which consists of a multi-point connector having an internal embedded integrated circuit. The contact arrangement contains contacts to a liquid crystal display cell, and external terminals to appropriate circuitry. The contact arrangement can be plugged into the side of the liquid crystal display cell in order to remain outside the display or illumination zone. The embedded integrated circuit is located in the immediate vicinity of the contacts from the liquid crystal cell inserted into the multi-point connector. By this means the electrical losses and outlay on the connections are considerably reduced.