Abstract: A method of managing the power consumed by a hard disk drive in a portable computer. The first step consists of measuring the work load placed on the hard disk drive by a particular computer, a particular application and a particular user. The next step is to determine the average power consumed in the disk drive in the active state and in a lower power state for a series of wait times. The next step is to determine the total average power consumed by the disk drive for both states for the series of wait times. The next step is to determine the wait time at which the total average power consumed by the disk drive in minimum. The final step is to set the wait time at which the disk drive operates to the previously determined minimum wait time.

Abstract: A digital communication system using a frequency-independent, high data transmission rate, self-clocking, d.c. balanced data encoding technique. The encoding technique converts two NRZ data bits into a pulse or pulse-pair. The form of the pulse or pulse-pair representing the encoded data bit-pair depends upon the average d.c. level of the previously transmitted pulses. Each pulse of a pulse-pair has a fixed width. The receiver is activated by the leading edge of a transmitted pulse-pair and samples the pulse-pair at points in time determined by the known fixed width of the pulses. The sampled pulse-pairs are then converted into NRZ data bit-pairs. Proper functioning of the receiver does not rely upon the rate upon which the data is transferred. A high data rate is achieved by encoding two bits of data in every pulse or pulse-pair transmitted.

Abstract: A computer system having a memory card for storing data that is capable of being removed and reinserted and also having the capability of safeguarding the data stored thereon. A passward is stored on the memory card. The memory card is set in a secure mode to prevent unauthorized access to the data stored on the memory card. Once the memory card is set in secure mode, it remains in secure mode, even when removed from the computer system and subsequently inserted back into that or another computer system. Access to the data is permitted when the memory card is set in secure mode only if a valid password is provided to the memory card.

Abstract: A secondary storage facility having a drive and a controller employing multiple error recovery techniques; the controller signals the drive to try such techniques in sequence, according to descending a priori probability of success. The controller does not know or need to know the details of the error recovery procedures.

Abstract: In a system including a plurality of mass storage devices at least one of which includes first and second ports, a plurality of controllers and cables coupling the ports to various ones of the controllers and in which each device can only be on-line through one port at a time, state information is sent from the on-line port of each device to a first controller to which it is coupled until a predetermined command from the controller to the on-line port is sent by the first controller. The device responds to the predetermined command by discontinuing the sending of state information from the on-line port to the first controller, and sending a state available signal from the other port to the second controller while maintaining the actual state of said device unchanged, permitting the other controller to interrogate the device as an aid in determining system topology.

Abstract: A radial bus for use in a secondary storage subsystem, between a mass storage drive and controller. The bus has four unidirectional bit-serial channels, two for carrying signals from drive to controllers. One channel carries real-time drive state information to the controller; another carries real-time controller state information to the drive. The state information is a sequence of multiplexed bits sent in continuous repetition. Most status variables are represented as a single bit in a specific place in the sequence; the set of status variables defining drive state or controller state, as the case may be, is thus provided by a sequence of bits. When such a bit changes state, a potential change of status has occurred; the change is required to persist some number of repetition of the sequence before the state change is recognized, to avoid spuriously signalling a state change.

Abstract: In a data processing system including a host computer and a secondary storage system that includes a controller and a mass storage device, the device stores information regarding the physical and logical characteristics of a disk drive associated with the device. In response to a command from the controller, the device produces a signal or signals which provide information to the controller regarding the physical and logical characteristics of the disk drive. The physical and logical characteristics include the drive bit transfer rate and subunit characteristics.

Abstract: A self-clocking encoding technique for synchronous transmission of digital signals, and apparatus therefor. In an exemplary embodiment, the encoding technique utilizes relatively positive and negative pulses of fixed, predetermined duration. For electrical pulses, the point of reference is preferably a zero baseline. At the leading edge LE.sub.i of the i.sup.th bit cell, the value of the i.sup.th bit is encoded as a positive pulse (e.g., 82A) in the case of a logical "1" or a negative pulse (e.g., 82B) in the case of a logical "0". Further, the next subsequent (i.e., (i+l).sup.th bit has the same value, a pulse (e.g., 82D) of the opposite polarity is injected into the i.sup.th bit cell after the leading edge pulse. Thus, positive and negative pulses alternate and the information content of the encoded signal has no d.c. component; this facilitates a.c. coupling. Further, the encoding technique is bit-rate (i.e., frequency-) independent and usable over a wide range of bit transfer rates.

Abstract: In a feedback control system wherein data pulses also establish timing coordination between the data and the processing devices, two delay circuits are provided to extract the synchronized clock pulses from the coded incoming signal. This enables relative digital decoding and ensures a precise data transfer to a computer interface. One of the delay circuits enables a data reconditioner circuit to buffer the data and eliminates data peak shifting. The reconditioned data is provided to a coincident circuit which selectively transfers the data to a computer interface and to a phase difference detector. The other delay circuit provides to the phase difference detector a second input corresponding in time to the coded incoming data pulses. The detector's output generates a DC error voltage which synchronizes a voltage controlled oscillator (VCO). The outputs of the VCO are clock pulses in phase with the coded incoming signals.