Patents by Inventor Peter Thieme

Peter Thieme has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090142916
    Abstract: On aspect is a method to manufacture an integrated circuit including a reshaping process of the wafer edge region and an apparatus to perform the reshaping process.
    Type: Application
    Filed: November 29, 2007
    Publication date: June 4, 2009
    Applicant: Qimonda AG
    Inventors: Heike Prenz, Peter Thieme, Peter Lahnor
  • Patent number: 7129173
    Abstract: A semiconductor substrate is provided, on which there is arranged a first layer, a second layer and a third layer. The third layer is, for example, a resist mask that is used to pattern the second layer. The second layer is, for example, a patterned hard mask used to pattern the first layer. Then, the third layer is removed and a fourth layer is deposited. The fourth layer is, for example, an insulator that fills the trenches which have been formed in the first layer. Then, the fourth layer is planarized by a CMP step. The planarization is continued and the second layer, which is, for example, a hard mask, is removed from the first layer together with the fourth layer. The fourth layer remains in place in a trench which is arranged in the first layer.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: October 31, 2006
    Assignee: Infineon Technologies AG
    Inventors: Heike Drummer, Franz Kreupl, Annette Sänger, Manfred Engelhardt, Bernhard Sell, Peter Thieme
  • Publication number: 20040048479
    Abstract: A semiconductor substrate is provided, on which there is arranged a first layer, a second layer and a third layer. The third layer is, for example, a resist mask that is used to pattern the second layer. The second layer is, for example, a patterned hard mask used to pattern the first layer. Then, the third layer is removed and a fourth layer is deposited. The fourth layer is, for example, an insulator that fills the trenches which have been formed in the first layer. Then, the fourth layer is planarized by a CMP step. The planarization is continued and the second layer, which is, for example, a hard mask, is removed from the first layer together with the fourth layer. The fourth layer remains in place in a trench which is arranged in the first layer.
    Type: Application
    Filed: August 27, 2003
    Publication date: March 11, 2004
    Inventors: Heike Drummer, Franz Kreupl, Annette Sanger, Manfred Engelhardt, Bernhard Sell, Peter Thieme
  • Patent number: 6559547
    Abstract: The semiconductor structure has a layer structure formed from a metalization layer and a dielectric layer. The metalization layer is patterned and has contact areas. The dielectric layer is composed of a depositable material and covers the metalization layer. The contact areas are formed from many contiguous individual structures, which are so narrow that the depositable material does not form, over the individual structures, any areas which run parallel to the metalization layer. The grid of contiguous individual structures forms a contact area which causes dielectric layer elevations which are particularly low and therefore easy to planarize.
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: May 6, 2003
    Assignee: Infineon Technologies AG
    Inventors: Matthias Uwe Lehr, Albrecht Kieslich, Peter Thieme, Lars Voland
  • Patent number: 4000147
    Abstract: New anhydro-2-mercapto-1,3,4-thiadiazolium hydroxides substituted in the 4- and 5-position, their manufacture and their use as medicaments.
    Type: Grant
    Filed: February 10, 1975
    Date of Patent: December 28, 1976
    Assignee: BASF Aktiengesellschaft
    Inventors: August Amann, Horst Koenig, Peter Thieme, Hubert Giertz, Rolf Kretzschmar