Abstract: The characteristic impedance of a surface pad is manipulated by reticulating the pad and filling the spaces with a dielectric material, providing an inductive element in the coupling of the surface pad to an underlying ground pad of a ground plane, or a combination of these approaches. In appropriate embodiments, acceptable signal trace routing paths will exist in an embedded signal layer under the ground plane and crossing under the surface pad. Other embodiments are also described and claimed.

Abstract: The characteristic impedance of a surface pad is manipulated by reticulating the pad and filling the spaces with a dielectric material, providing an inductive element in the coupling of the surface pad to an underlying ground pad of a ground plane, or a combination of these approaches. In appropriate embodiments, acceptable signal trace routing paths will exist in an embedded signal layer under the ground plane and crossing under the surface pad. Other embodiments are also described and claimed.

Abstract: The characteristic impedance of a surface pad is manipulated by reticulating the pad and filling the spaces with a dielectric material, providing an inductive element in the coupling of the surface pad to an underlying ground pad of a ground plane, or a combination of these approaches. In appropriate embodiments, acceptable signal trace routing paths will exist in an embedded signal layer under the ground plane and crossing under the surface pad. Other embodiments are also described and claimed.

Abstract: Plated through holes pass through clearances in a ground plane of a circuit board. A conductive collar/spoke arrangement is constructed on the ground plane adjacent the clearance, to provide an inductive component to the coupling between a plated through hole and the ground plane. The inductive component impedes the transfer of high-frequency noise between the through hole and the ground plane. Other embodiments are also described and claimed.

Abstract: A method of manufacture of an integrated MOS semiconductor array for the low-frequency range having MOS components and circuit paths arranged on a semiconductor substrate. Exposed surfaces between the circuit paths are made hydrophobic by germinating with hexamethyl disilazane ((CH.sub.3).sub.3 SiNHSi(CH.sub.3).sub.3), so that the occurrence of leakage currents is avoided. In addition, in an integrated MOS semiconductor array in which the MOS components and the circuit path are covered with a protective layer, the surface of this protective layer is made hydrophobic. As a result, both leakage currents and parasitic capacitances are prevented.