Abstract: Systems, methods, and other embodiments associated with providing real time closed loop control of memory access are described. According to one embodiment, a method includes accessing a memory of a computing device during real time operation of the computing device and detecting bit errors associated with the accessing of the memory. The method also includes generating a performance metric based on, at least in part, the detected bit errors during the real time operation of the computing device. The method further includes adjusting a setting of at least one timing element, of a plurality of timing elements of a physical layer of the computing device, based on the performance metric during the real time operation of the computing device to maintain a determined memory access performance.

Abstract: System and methods for storing data encoded with error information in a storage medium are provided. A binary data and an encoded binary error signals are received. The encoded binary error signal includes information that represents occurrence of errors in the binary data signal. The binary data and encoded binary error signals are encoded to generate a binary codeword signal. Bits of the binary codeword signal that represent coding information and the binary data signal are extracted. The extracted bits of the binary codeword signal are stored in a first storage medium. The binary packed data signal is retrieved from the first storage device and decoded to recover the binary data signal and a syndrome. Error information corresponding to the encoded binary error signal may be determined based on the syndrome.

Abstract: A formatted data unit that was transmitted by a transmitter is received at a receiver. Received signal points are determined based on the received formatted data unit. Actual transmitted signal points corresponding to the received formatted data unit is determined at the receiver based on information known a priori by the receiver. An error is determined between the received signal points and the actual transmitted signal points determined at the receiver. An indicator of impulse noise is generated based on the error.

Abstract: A transform calculator includes a plurality of memories. A memory mapping rules module is configured to apportion points of a discrete time domain sequence among the plurality of memories. A pipelined data path is configured to iteratively process pairs of the points of the discrete time domain sequence received from the plurality of memories. A control module is configured to select the pairs of the points in the plurality of memories for processing by the pipelined data path, wherein only one point of each of the pairs of the points is selected at a given time.

Abstract: System and methods for storing data encoded with error information in a storage medium are provided. A binary data and an encoded binary error signals are received. The encoded binary error signal includes information that represents occurrence of errors in the binary data signal. The binary data and encoded binary error signals are encoded to generate a binary codeword signal. Bits of the binary codeword signal that represent coding information and the binary data signal are extracted. The extracted bits of the binary codeword signal are stored in a first storage medium. The binary packed data signal is retrieved from the first storage device and decoded to recover the binary data signal and a syndrome. Error information corresponding to the encoded binary error signal may be determined based on the syndrome.

Abstract: A formatted data unit that was transmitted by a transmitter is received at a receiver. Received signal points are determined based on the received formatted data unit. Actual transmitted signal points corresponding to the received formatted data unit is determined at the receiver based on information known a priori by the receiver. An error is determined between the received signal points and the actual transmitted signal points determined at the receiver. An indicator of impulse noise is generated based on the error.

Abstract: A system includes a linked-list generator module that generates a linked list of tones based on tones and bit loads of the respective tones in a digital subscriber line (DSL) communication system, a trellis encoder module that encodes data bits associated with respective ones of the tones, and a bit application module that communicates the data bits to the trellis encoder module based on the linked list.

Abstract: Circuit, method, and computer program for reordering data units of a data block in accordance with a first pre-determined function. The method includes, for each data unit of the data block—(i) generating an address corresponding to a memory location of a single-port memory module into which the data unit is to be stored, and (ii) storing the data unit in the memory location based on the address generated for the data unit. Each address is generated in accordance with the first pre-determined function, and each memory location of the single-port memory has a different delay associated with the memory location. The method further includes reading each data unit out of the single-port memory in accordance with the first pre-determined function, wherein data units of the data block are reordered based on each different delay associated with each memory location.

Abstract: Apparatus and methods are described for detecting an impulse noise and for controlling frequency domain equalizer (FEQ) coefficient updating in response to impulse noise detection. Upon detection of the impulse noise, FEQ coefficient updating may immediately be frozen to prevent the FEQ coefficients from being corrupted by the impulse noise. The FEQ coefficient updating may be resumed after the impulse has ended, allowing for normal operation and channel detection.

Abstract: A system including a forecasting module, a decoder module, and an error detecting module. The forecasting module is configured to forecast a number of erasures in an input signal, where the erasures include information about errors in the input signal due to a burst error. The decoder module is configured to decode codewords received in the input signal based on the erasures in response to the number of the erasures being less than or equal to a predetermined threshold. The decoder module is configured to not decode the codewords based on the erasures in response to the number of the erasures being greater than the predetermined threshold. The error detecting module is configured to (i) detect the burst error and (ii) decode the codewords in response to the decoder module not decoding the codewords due to the number of the erasures being greater than the predetermined threshold.

Abstract: An erasure forecasting system includes a control module, an erasure feed-forward module, and an erasure decoder. The control module selects erasure parameters and determines error-detection thresholds for forecasting erasure in an input signal. The erasure feed-forward module receives the input signal, forecasts erasure in the input signal, generates an erasure feed-forward signal based on the erasure parameters and the error-detection thresholds, and generates codewords based on the erasure feed-forward signal and the input signal. The erasure decoder determines that the input signal is one of erroneous and not erroneous based on the erasure feed-forward signal.

Abstract: A system includes M memories, wherein a first mapping assigns each point of an N-point input sequence to one of the M memories. A pipelined data path receives an input from each of the M memories, stores an output to each of the M memories, and iteratively processes pairs of points of the N-point input sequence. A control module designates the pairs of points from the M memories for processing by the data path, wherein only one point of each of the pairs is designated at one time.

Abstract: A circuit is provided for performing interleaving and deinterleaving functions in a digital communication system. The circuit includes a single-port memory that reads first data units from a first interleaved sequence of address locations to generate a first data stream and that writes second data units from a second data stream to the address locations. A first address generator module communicates with the single-port memory and generates a first interleaved sequence of addresses that correspond to the address locations and correspond to one of an interleaving function and deinterleaving function between the first data stream and the second data stream.

Abstract: In a method and apparatus for selective convolutional interleaving or de-interleaving of symbols or data bits, a plurality of segments are defined in random access memory, with each segment including a different number of locations for storing symbols. Previously stored symbols are sequentially read out of current locations in the segments respectively, and new symbols are read into the current locations. Next locations in the segments are redesignated as current locations respectively, and the operation is repeated until all of the symbols have been interleaved or de-interleaved. The first location in each segment is designated by a respective segment pointer. The current and next locations are designated as relative offset pointers from the segment pointers, and these locations are incremented by incrementing the offset pointers. Interleaving or de-interleaving operation is determined by the direction in which the segments are sequentially selected for the read/write operations.