Patents by Inventor Peter VanDerVoorn

Peter VanDerVoorn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7517768
    Abstract: A bipolar transistor with a SiGe:C film and a seed layer forming beneath the SiGe:C film and methods of making same. The method includes placing a substrate in a reactor chamber and introducing a silicon source gas into the reactor chamber to form a silicon seed layer. The reactor chamber is maintained at a pressure below 45 Torr and a temperature between about 700° C. and 850° C. After the seed layer is formed, the silicon source gas is stopped. The reactor chamber is then simultaneously adjusted to a pressure between about 70 Torr and 90 Torr and a temperature between about 600° C. and 650° C. The silicon source gas, a germanium source gas, and a carbon source gas are introduced to form the SiGe:C film on the seed layer.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: April 14, 2009
    Assignee: Intel Corporation
    Inventors: Ravindra Soman, Anand Murthy, Peter VanDerVoorn, Shahriar Ahmed
  • Publication number: 20060148150
    Abstract: Higher mobility transistors may be achieved by removing a dummy metal gate electrode as part of a replacement metal gate process and doping the exposed channel region after source and drains have already been formed. As a result, a retrograde doping profile may be achieved in some embodiments in the channel region which is not adversely affected by subsequent high temperature processing. For example, after already forming the source and drains and thereafter doping the channel, temperature regimes greater than 900° C. may be avoided.
    Type: Application
    Filed: January 3, 2005
    Publication date: July 6, 2006
    Inventors: Jack Kavalieros, Peter Vandervoorn, Kelin Kuhn, Justin Brask, Mark Doczy, Matthew Metz, Suman Datta, Robert Chau
  • Publication number: 20050266654
    Abstract: A method includes forming a first and a second semiconductor region which are joined at a semiconductor junction. The first and second semiconductor regions are truncated with an isolation trench, with an end of the semiconductor junction being disposed at the isolation trench. The isolation trench is at least partially filled with an insulation material. A salicide-blocking barrier is formed over a first surface portion of the first semiconductor region proximally disposed relative to the isolation trench. An amorphization implant is implanted in a second surface portion of the first semiconductor region distally disposed relative to the isolation trench. A salicide layer is formed in the amorphization implant.
    Type: Application
    Filed: May 27, 2004
    Publication date: December 1, 2005
    Inventors: Michael Hattendorf, Peter Vandervoorn
  • Publication number: 20040192002
    Abstract: A bipolar transistor with a SiGe:C film and a seed layer forming beneath the SiGe:C film and methods of making same. The method includes placing a substrate in a reactor chamber and introducing a silicon source gas into the reactor chamber to form a silicon seed layer. The reactor chamber is maintained at a pressure below 45 Torr and a temperature between about 700° C. and 850° C. After the seed layer is formed, the silicon source gas is stopped. The reactor chamber is then simultaneously adjusted to a pressure between about 70 Torr and 90 Torr and a temperature between about 600° C. and 650° C. The silicon source gas, a germanium source gas, and a carbon source gas are introduced to form the SiGe:C film on the seed layer.
    Type: Application
    Filed: March 31, 2003
    Publication date: September 30, 2004
    Inventors: Ravindra Soman, Anand Murthy, Peter VanDerVoorn, Shahriar Ahmed