Abstract: Methods and systems are disclosed to generate a data map for a data storage device. A data map may be generated by scanning, during a power-on initialization process, data units of data stored on a data storage medium of a data storage device. The scanning may start from a selected data unit and proceed through the data units in an order opposite to a write order to identify a first data unit that is not fully erased. Also. an error recovery status of the first data unit may be determined based on an error correction code. A likely erased status of the first data unit may be assigned when the determined error recovery status is unrecoverable.

Abstract: Methods and systems are disclosed to generate a data map for a data storage device. A data map may be generated by scanning, during a power-on initialization process, data units of data stored on a data storage medium of a data storage device. The scanning may start from a selected data unit and proceed through the data units in an order opposite to a write order to identify a first data unit that is not fully erased. Also. an error recovery status of the first data unit may be determined based on an error correction code. A likely erased status of the first data unit may be assigned when the determined error recovery status is unrecoverable.

Abstract: An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The interleaver has adder circuits that generate output address sequences associated with each data sub-block. The interleaver has memory that stores the data sub-blocks at addresses controlled by the input address sequence. The memory reproduces each data sub-block in an interleaved sequence controlled by the associated output address sequence. The interleaver has an output multiplexer that assembles the interleaved sequences to provide an interleaver output.

Abstract: A second stage SOVA detector comprises a dynamic state reordering block with inputs that receive absolute state domain data from a first stage SOVA detector. The second stage SOVA detector provides relative state domain data outputs and selection bit outputs. The second stage SOVA detector comprises pipeline registers. The pipeline registers receive the relative state domain data outputs and the selection bit outputs and provide pipelined outputs. The second stage SOVA detector comprises a reliability update-register exchange unit receiving the pipelined outputs and providing detected data bits and reliabilities.