Patents by Inventor Peter Verheyen
Peter Verheyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20260005091Abstract: Electronic-photonic systems including an integrated device, and methods for manufacturing the integrated device, are provided. In one aspect, the integrated device includes an electronic integrated circuit (EIC) and a photonic integrated circuit (PIC) bonded and electrically connected to the EIC. The PIC includes a waveguide and a heater configured to heat the waveguide. The integrated device includes one or more cavities arranged between the heater and the EIC for thermally isolating the heater from the EIC.Type: ApplicationFiled: June 26, 2025Publication date: January 1, 2026Inventors: David Coenen, Herman Oprins, Joris Van Campenhout, Peter Verheyen, Yoojin Ban, Minkyu Kim, Filippo Jacopo Ferraro, Robert Miller, Philippe Absil, Dimitrios Velenis
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Publication number: 20250300427Abstract: The disclosure relates to a method for forming electrical connections in devices with a top surface having an electrical path and a cavity for a die. The method includes creating a (e.g., substantially) continuous interconnect layer from the cavity's bottom to the electrical path, overcoming topographical hurdles. The method also relates to a corresponding device.Type: ApplicationFiled: March 17, 2025Publication date: September 25, 2025Inventors: Negin Golshani, Peter Verheyen, Joris Van Campenhout
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Patent number: 11600735Abstract: A method is provided for fabricating an avalanche photodiode (APD) device, in particular, a separate absorption charge multiplication (SACM) APD device. The method includes forming a first contact region and a second contact region in a semiconductor layer. Further, the method includes forming a first mask layer above at least a first contact region of the semiconductor layer adjacent to the first contact region, and forming a second mask layer above and laterally overlapping the first mask layer. Thereby, a mask window is defined by the first mask layer and the second mask layer, and the first mask layer and/or the second mask layer are formed above a second contact region of the semiconductor layer adjacent to the second contact region.Type: GrantFiled: July 8, 2021Date of Patent: March 7, 2023Assignee: IMEC VZWInventors: Ashwyn Srinivasan, Peter Verheyen, Philippe Absil, Joris Van Campenhout
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Publication number: 20220013682Abstract: A method is provided for fabricating an avalanche photodiode (APD) device, in particular, a separate absorption charge multiplication (SACM) APD device. The method includes forming a first contact region and a second contact region in a semiconductor layer. Further, the method includes forming a first mask layer above at least a first contact region of the semiconductor layer adjacent to the first contact region, and forming a second mask layer above and laterally overlapping the first mask layer. Thereby, a mask window is defined by the first mask layer and the second mask layer, and the first mask layer and/or the second mask layer are formed above a second contact region of the semiconductor layer adjacent to the second contact region.Type: ApplicationFiled: July 8, 2021Publication date: January 13, 2022Inventors: Ashwyn Srinivasan, Peter Verheyen, Philippe Absil, Joris Van Campenhout
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Patent number: 9482816Abstract: Semiconductor photonics devices for coupling radiation to a semiconductor waveguide are described. An example photonics device comprises a semiconductor-on-insulator substrate comprising a semiconductor substrate, a buried oxide layer positioned on top of the semiconductor substrate, and the semiconductor waveguide on top of the buried oxide layer to which radiation is to be coupled. The example device also comprises a grating coupler positioned on top of the buried oxide layer and configured for coupling incident radiation to the semiconductor waveguide. The semiconductor substrate has a recessed portion at the backside of the semiconductor substrate for receiving incident radiation to be coupled to the semiconductor waveguide via the backside of the semiconductor substrate and the grating coupler.Type: GrantFiled: December 4, 2014Date of Patent: November 1, 2016Assignee: IMEC VZWInventors: Joris Van Campenhout, Philippe Absil, Peter Verheyen
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Patent number: 9159860Abstract: An avalanche photodetector element is disclosed for converting an optical signal to an electrical signal, comprising an input waveguide and a photodetector region, the photodetector region comprising at least one intrinsic region, at least one p-doped region and at least one n-doped region, the doped regions and the at least one intrinsic region forming at least one PIN-junction avalanche photodiode, the input waveguide and the photodetector region being arranged with respect to each other such that the optical signal conducted by the input waveguide is substantially conducted into the photodetector region to the PIN-junction avalanche photodiode, the PIN-junction avalanche photodiode converting the optical signal to an electrical signal, characterized in that the photodetector region comprises more than one p-doped region and/or n-doped region, whereby these p-doped regions and/or n-doped regions are physically arranged as an array.Type: GrantFiled: November 22, 2013Date of Patent: October 13, 2015Assignee: IMECInventors: Geert Hellings, Joris Van Campenhout, Peter Verheyen
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Publication number: 20150177459Abstract: Semiconductor photonics devices for coupling radiation to a semiconductor waveguide are described. An example photonics device comprises a semiconductor-on-insulator substrate comprising a semiconductor substrate, a buried oxide layer positioned on top of the semiconductor substrate, and the semiconductor waveguide on top of the buried oxide layer to which radiation is to be coupled. The example device also comprises a grating coupler positioned on top of the buried oxide layer and configured for coupling incident radiation to the semiconductor waveguide. The semiconductor substrate has a recessed portion at the backside of the semiconductor substrate for receiving incident radiation to be coupled to the semiconductor waveguide via the backside of the semiconductor substrate and the grating coupler.Type: ApplicationFiled: December 4, 2014Publication date: June 25, 2015Applicant: IMEC VZWInventors: Joris Van Campenhout, Philippe Absil, Peter Verheyen
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Patent number: 8741684Abstract: Disclosed are methods for co-integration of active and passive photonic devices on a planarized silicon-based photonics substrate. In one aspect, a method is disclosed that includes providing a planarized silicon-based photonics substrate comprising a silicon waveguide structure, depositing a dielectric layer over the planarized silicon-based photonics substrate, selectively etching the dielectric layer, thereby exposing at least a portion of the silicon waveguide structure, selectively etching the exposed portion of the silicon waveguide structure to form a template, using the silicon waveguide structure as a seed layer to selectively grow in the template a germanium layer that extends above the dielectric layer, and planarizing the germanium layer to form a planarized germanium layer, wherein the planarized germanium layer does not extend above the dielectric layer.Type: GrantFiled: May 8, 2012Date of Patent: June 3, 2014Assignees: IMEC, Universiteit GentInventors: Wim Bogaerts, Joris Van Campenhout, Peter Verheyen, Philippe Absil
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Publication number: 20140138787Abstract: An avalanche photodetector element is disclosed for converting an optical signal to an electrical signal, comprising an input waveguide and a photodetector region, the photodetector region comprising at least one intrinsic region, at least one p-doped region and at least one n-doped region, the doped regions and the at least one intrinsic region forming at least one PIN-junction avalanche photodiode, the input waveguide and the photodetector region being arranged with respect to each other such that the optical signal conducted by the input waveguide is substantially conducted into the photodetector region to the PIN-junction avalanche photodiode, the PIN-junction avalanche photodiode converting the optical signal to an electrical signal, characterized in that the photodetector region comprises more than one p-doped region and/or n-doped region, whereby these p-doped regions and/or n-doped regions are physically arranged as an array.Type: ApplicationFiled: November 22, 2013Publication date: May 22, 2014Applicant: IMECInventors: Geert Hellings, Joris Van Campenhout, Peter Verheyen
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Patent number: 8492273Abstract: A method is disclosed comprising providing a substrate comprising an insulating material and a second semiconductor material and pre-treating the substrate with a plasma produced from a gas selected from the group consisting of a carbon-containing gas, a halogen-containing gas, and a carbon-and-halogen containing gas. The method further comprises depositing a first semiconductor material on the pre-treated substrate by chemical vapor deposition, where the first semiconductor material is selectively deposited on the second semiconductor material. The method may be used to manufacture a semiconducting device, such as a microelectromechanical system device, or to manufacture a semiconducting device feature, such as an interconnect.Type: GrantFiled: August 1, 2011Date of Patent: July 23, 2013Assignee: IMECInventors: George Bryce, Simone Severi, Peter Verheyen
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Publication number: 20120288971Abstract: Disclosed are methods for co-integration of active and passive photonic devices on a planarized silicon-based photonics substrate. In one aspect, a method is disclosed that includes providing a planarized silicon-based photonics substrate comprising a silicon waveguide structure, depositing a dielectric layer over the planarized silicon-based photonics substrate, selectively etching the dielectric layer, thereby exposing at least a portion of the silicon waveguide structure, selectively etching the exposed portion of the silicon waveguide structure to form a template, using the silicon waveguide structure as a seed layer to selectively grow in the template a germanium layer that extends above the dielectric layer, and planarizing the germanium layer to form a planarized germanium layer, wherein the planarized germanium layer does not extend above the dielectric layer.Type: ApplicationFiled: May 8, 2012Publication date: November 15, 2012Applicants: Universiteit Gent, IMECInventors: Wim Bogaerts, Joris Van Campenhout, Peter Verheyen, Philippe Absil
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Publication number: 20120034762Abstract: A method is disclosed comprising providing a substrate comprising an insulating material and a second semiconductor material and pre-treating the substrate with a plasma produced from a gas selected from the group consisting of a carbon-containing gas, a halogen-containing gas, and a carbon-and-halogen containing gas. The method further comprises depositing a first semiconductor material on the pre-treated substrate by chemical vapor deposition, where the first semiconductor material is selectively deposited on the second semiconductor material. The method may be used to manufacture a semiconducting device, such as a microelectromechanical system device, or to manufacture a semiconducting device feature, such as an interconnect.Type: ApplicationFiled: August 1, 2011Publication date: February 9, 2012Applicant: IMECInventors: George Bryce, Simone Severi, Peter Verheyen
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Patent number: 7799664Abstract: One inventive aspect relates to a method of selective epitaxial growth of source/drain (S/D) areas. The method includes providing a substrate having a first and a second substrate area, the first area including at least one gate stack. The method includes applying a poly-Si or poly-SiGe top layer on the substrate, the top layer being etchable with the same etch chemistry as the substrate. The method includes removing the poly-Si or poly-SiGe top layer from the first area selectively towards the poly-Si or poly-SiGe top layer in the second area. The method includes removing simultaneously the poly-Si or poly-SiGe top layer on the second area and at least a part of the substrate in the S/D areas of the first area selectively to the gate stack. The method includes performing a selective epitaxial growth of S/D areas in the first area.Type: GrantFiled: December 22, 2006Date of Patent: September 21, 2010Assignee: IMECInventors: Peter Verheyen, Rita Rooyackers, Denis Shamiryan
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Publication number: 20070237728Abstract: This invention relates to a method for bleaching teeth that have been discoloured by a staining agent. The method comprises the steps of coating an area of at least one tooth to be bleached with a dental bleaching composition and irradiating the coated area with laser energy for a predetermined period of time to activate an oxidising agent contained in the bleaching composition, the activated oxidising agent being capable of reacting with the staining agent to at least partly discolour the staining agent. In the method of this invention use is made of a laser emitting laser energy of a wave length capable of inducing a photochemical generation of radicals of the oxidising agent, which radicals in turn are capable of reacting with the staining agent to form a compound that is free of a conjugated electron system capable of absorbing visible light.Type: ApplicationFiled: June 15, 2007Publication date: October 11, 2007Applicant: HIGH TECH LASERInventor: Peter VERHEYEN
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Publication number: 20070148860Abstract: One inventive aspect relates to a method of selective epitaxial growth of source/drain (S/D) areas. The method comprises providing a substrate of semiconductor material, the substrate comprising a first substrate area and a second substrate area, the first area comprising at least one gate stack. The method further comprises applying at least a poly-Si or poly-SiGe top layer on the substrate, the top layer being etchable with the same etch chemistry as the substrate. The method further comprises removing the poly-Si or poly-SiGe top layer from the first area of the substrate selectively towards the poly-Si or poly-SiGe top layer in the second substrate area. The method further comprises removing simultaneously the poly-Si or poly-SiGe top layer on the second substrate area and at least a part of the substrate in the S/D areas of the first substrate area selectively to the at least one gate stack. The method further comprises performing a selective epitaxial growth of S/D areas in the first substrate area.Type: ApplicationFiled: December 22, 2006Publication date: June 28, 2007Inventors: Peter Verheyen, Rita Rooyackers, Denis Shamiryan