Abstract: A vector processing unit contains an operation cache and a separate micro-op cache. The operation cache tracks state and logic of instructions, and is responsible for splitting instructions into micro-ops. The micro-op cache tracks state and logic of micro-ops. Having a separate micro-op cache provides power and area benefits, as well as allowing instructions to be split out of order.

Abstract: When an instruction is received, the instruction checks against older “in-flight” instructions for hazards, and stores a hazard flag in a control storage entry. An instruction will not start executing while the hazard flag is set. When the older instruction executes and produces a result to a register, it clears the hazard for the current instruction. The current instruction can start executing when no hazards remain.

Abstract: A handshaking protocol is implemented between a control unit, a vector processing unit (VPU) and a load-store unit (LSU). Micro-ops of an instruction will only be executed by the LSU if it is guaranteed not to generate an exception and no earlier micro-ops will generate an exception. The handshaking protocol guarantees this using signals passed between the control unit, VPU and LSU.

Abstract: A computer-implemented method for performing a vector bitwise rotation, wherein a processing system comprises a byte-wise anything-to-anything mux and one or more bitwise right shifters, wherein the byte-wise anything-to-anything mux includes a plurality of byte-sized inputs and a plurality of byte-sized outputs, each input being associated with a respective input position and each output being associated with a respective output position. A combination of a byte-wise anything-to-anything mux and one or more bitwise shifts is used to perform vector bitwise rotations, with even and odd elements of the vector operated on separately.

Abstract: Segment load operations are performed by processing data through an anything-to-anything mux, and sections writing elements to respective storage locations based on corresponding indices of the elements and the storage locations. Once all of the elements are loaded into the correct storage location, each location is read again with the elements of that storage location being sent through the mux, arranged) into the correct order, and written back to the same register.

Abstract: A memory attribute structure, which is configurable, is used when processing memory access transactions through an execution path of a processing system. The memory attribute structure includes one or more memory address entries. The entries are configurable. Each memory address entry comprising a respective memory address range mapped to a respective priority level of a set of priority levels. A central processing unit is configured to use the memory attribute structure to determine respective priority levels mapped to respective memory addresses of respective memory access transaction, and process the respective memory access transactions based on the respective priority levels.

Abstract: A memory attribute structure comprises one or more memory address entries. Each memory address entry comprising a respective memory address range mapped to a respective priority level. The memory attribute table is used when processing a memory access transaction through an execution path of a processing system. During said processing, a memory address of the memory access transaction is determined. The memory attribute structure is used to determine a priority level mapped to the determined memory address, and the memory access transaction is processed based on the determined priority level.

Abstract: Apparatuses comprising processing circuitry, a first wakeup interrupt controller connected to the processing circuitry via a first interface, and a second wakeup interrupt controller connected to the processing circuitry via a second interface, and methods of operating such apparatuses, are disclosed. Prior to the processing circuitry entering a low power state, information defining at least one wakeup event is transferred from the processing circuitry to a selected wakeup interrupt controller. Whilst the processing circuitry is in the low power state, the selected wakeup interrupt controller receives event indications. If one of these event indications is a defined wakeup event, then the processing circuitry is caused to exit the low power state.

Abstract: Apparatuses comprising data processing circuitry and a wakeup interrupt controller and methods of operating the apparatuses are disclosed. Prior to the processing circuitry entering a low power state, indications of pending interrupts are transferred to the wakeup interrupt controller. Further indications of interrupts received whilst the processing circuitry is in the low power state may be accumulated in the wakeup interrupt controller. When the wakeup interrupt controller receives a wakeup signal, the indications of pending interrupts are transferred to the processing circuitry and the processing circuitry exits the low power state.

Abstract: An apparatus comprises a non-associative memory comprising a plurality of storage locations, and error recovery storage to store at least one error recovery entry providing a recovery value for a corresponding storage location of the non-associative memory. Control circuitry is responsive to a non-associative memory read request specifying a target address of a storage location of the non-associative memory, when the error recovery storage includes a valid matching error recovery entry for which the corresponding storage location is the storage location identified by the target address, to return the recovery value stored in the valid matching error recovery entry as a response to the non-associative memory read request, instead of information stored in the storage location identified by the target address. This enables the apparatus to continue to function even if hard errors occur in a storage location of the non-associative memory.

Abstract: Apparatuses comprising processing circuitry, a first wakeup interrupt controller connected to the processing circuitry via a first interface, and a second wakeup interrupt controller connected to the processing circuitry via a second interface, and methods of operating such apparatuses, are disclosed. Prior to the processing circuitry entering a low power state, information defining at least one wakeup event is transferred from the processing circuitry to a selected wakeup interrupt controller. Whilst the processing circuitry is in the low power state, the selected wakeup interrupt controller receives event indications. If one of these event indications is a defined wakeup event, then the processing circuitry is caused to exit the low power state.

Abstract: Apparatuses comprising data processing circuitry and a wakeup interrupt controller and methods of operating the apparatuses are disclosed. Prior to the processing circuitry entering a low power state, indications of pending interrupts are transferred to the wakeup interrupt controller. Further indications of interrupts received whilst the processing circuitry is in the low power state may be accumulated in the wakeup interrupt controller. When the wakeup interrupt controller receives a wakeup signal, the indications of pending interrupts are transferred to the processing circuitry and the processing circuitry exits the low power state.

Abstract: An apparatus comprises a non-associative memory comprising a plurality of storage locations, and error recovery storage to store at least one error recovery entry providing a recovery value for a corresponding storage location of the non-associative memory. Control circuitry is responsive to a non-associative memory read request specifying a target address of a storage location of the non-associative memory, when the error recovery storage includes a valid matching error recovery entry for which the corresponding storage location is the storage location identified by the target address, to return the recovery value stored in the valid matching error recovery entry as a response to the non-associative memory read request, instead of information stored in the storage location identified by the target address. This enables the apparatus to continue to function even if hard errors occur in a storage location of the non-associative memory.