Abstract: A linear lighting device may include an elongated housing that defines a cavity. The linear lighting device may include plurality of emitter printed circuit boards configured to be received within the cavity. Each of the plurality of emitter printed circuit boards may include a plurality of emitter modules mounted thereto. Each of the plurality of emitter printed circuit boards may include a control circuit configured to control the plurality of emitter modules mounted to the respective emitter printed circuit board based on receipt of one or more messages. The linear lighting device may include a total internal reflection lens for each of the plurality of emitter printed circuit boards. The total internal reflection lens may be configured to diffuse light emitted by the emitter modules of the plurality of emitter printed circuit boards.

Abstract: A linear lighting device may include an elongated housing that defines a cavity. The linear lighting device may include plurality of emitter printed circuit boards configured to be received within the cavity. Each of the plurality of emitter printed circuit boards may include a plurality of emitter modules mounted thereto. Each of the plurality of emitter printed circuit boards may include a control circuit configured to control the plurality of emitter modules mounted to the respective emitter printed circuit board based on receipt of one or more messages. The linear lighting device may include a total internal reflection lens for each of the plurality of emitter printed circuit boards. The total internal reflection lens may be configured to diffuse light emitted by the emitter modules of the plurality of emitter printed circuit boards.

Abstract: A two-stage RF amplifier comprising first and second transistors arranged in cascode. An input stage includes a common source transistor having a gate terminal responsive to an input signal and an output stage includes a common gate transistor having a source terminal operatively connected to the drain terminal of the common source transistor. A shunt feedback network is arranged between a drain terminal of the common gate transistor and the gate terminal of the common source transistor. A source feedback network is arranged between the source terminal of the common source transistor and a reference potential. A common gate feedback network is arranged between the drain terminal of the common gate transistor and a gate terminal of the common gate transistor. And a termination feedback network is arranged in series between the reference potential and the gate terminal of the common gate transistor.