Abstract: A phase lock loop circuit comprises a variable frequency oscillator having a control input and an output, a divider having an input coupled with the output of the oscillator and an output coupled with the first input of a phase or frequency comparator. The comparator has a second input for a reference frequency (F.sub.REF) and an output coupled with the oscillator control input for providing a signal which is related to the difference in phase or frequency of the signals at the first and second inputs to effect phase locking of the oscillator to the reference signal. A detector provides a switching signal when the control signal falls outside a predetermined range and a switch in the phase lock loop is responsive to the switching signal to open the loop.

Abstract: An adjustable ratio divider comprises a controllable gate connected in series with a divider for passing a clock signal in pulse form whose frequency is to be divided. A means is provided for controlling the gate to subtract a selectable number (including zero) of clock pulses from the clock signal to control the division ratio of the divider.