Abstract: This invention provides a process within an optimizing compiler for transforming code to take advantage of update instructions available on some computer architectures. On architectures which implement some form of autoindexing instructions or addressing modes, this process will improve the code generated for looping constructs which manipulate arrays in memory. The process is achieved by selecting memory referencing instructions inside loops for conversion to update forms, modifying those instructions to an update form available on a particular processor, and applying an offset compensation to other memory referencing instructions in the loop so as to enable the program to still address the appropriate locations while using the available autoindexing instructions. The improved compiler and compiler process enables the compiler to convert those program instructions that would otherwise convert to autoindexing instructions not supported by the processor to autoindexing instructions that are supported.

Abstract: A method for performing floating point division is provided for producing a quotient having a mantissa of n bits. The method consists of the steps of accessing an initial guess of a reciprocal of the divisor from a table of divisor reciprocals, computing an initial estimate the quotient in a corresponding estimate from the initial estimate of the reciprocal, increasing the precision of the mantissa of the reciprocal estimate, quotient estimate, and remainder estimate by computing an error parameter and iteratively computing a current reciprocal estimate, a current quotient estimate and a current remainder estimate from the error parameter and the latest reciprocal estimate, quotient estimate and remainder estimates. Also, the step of increasing the precision is repeated until the quotient estimate and reciprocal estimate exceed n bits. Lastly, the final quotient is computed from the last current quotient estimate plus the last current reciprocal estimate times the last current remainder estimate.

Abstract: A computer program to be compiled is optimized prior to carrying out the final compilation. Subgraphs within the program are identified and examined for optimization beginning with the entire program as the largest subgraph. The number of entities in each subgraph which are relevant to each dimension of arrays used to represent data flow equations is determined. Next, the amount of memory required to contain the arrays is determined. If that memory requirement is within a predefined memory usage limit for the compilation, then a specified procedure of the compilation process is applied. If the memory requirement to contain the arrays exceeds the predefined memory usage limit for the compilation, the process is repeated for successively smaller subgraphs within the program in an attempt to find a subgraph to which the memory limits allow application of the specified procedure.

Abstract: A procedure for use in an optimizing compiler termed "reassociation" determines the preferred order of combining terms in a sum so as to produce loop invariant subcomputations, or to promote common subexpressions among several essential computations, by applying the associative law of addition. To achieve this, the requisite optimization of an object program or program segment, the following discrete steps must be performed after the strongly connected regions, USE and DEF chains have all been identified:1. Find the region constants and induction variables;2. Identify all of the essential computations;3. Write every essential computation as a sum of products;4. Exploit the use and DEF functions to substitute the definition of each operand R in an essential computation, if there is a unique computation of R in the strongly connected region and the defining operation is +, -, .times., or copy;5. Fix displacements;6.

Abstract: A method for improving the quality of code generated by a compiler in terms of execution time, object code space, or both. The method is applicable to computers that have a redundancy of instructions, in that the same operation exists in forms that operate between registers, between main storage locations, and between registers and main storage. The method selects the best form of each such instruction to use, for the context in which the instruction lies.

Abstract: A method for use during the optimizatin phase of an optimizing compiler for performing global common subexpression elimination and code motion which comprises:Determining the code `basis` for the object program which includes examining each basic block of code and determining the `basis` items on which each computation depends wherein `basis` items are defined as operands which are referenced in a basic block before being computed. The method next determines the "kill set" for each `basis` item. Following this UEX, DEX, and THRU are determined for each basic block using the previously determined `basis` and "kill set" information. AVAIL and INSERT are computed from UEX, DEX, and THRU, and appropriate code insertions are made at those locations indicated by the preceding step, and finally redundant code is removed using the AVAIL set.

Abstract: A method operable within an optimizing compiler to move certain range check instructions out of single entry strongly connected regions or loops and into linear regions of the instruction stream whereby computational efficiency is increased with no loss of program accuracy. The method comprises placing a range check trap instruction into the header node of the SCR provided there is only one conditional exit from the SCR, modifying the conditional exit test based on the value of the induction variable v, and inserting a new check at the loop exit point(s) to insure that the induction variable has reached the value it would have obtained in the original (unmodified) program.

Abstract: A method operable within an optimizing compiler for generating Basis items and Kill Sets for use during subsequent global common subexpressions elimination and code motion procedures. More particularly, the method comprises assigning a symbolic register to each non-basis element to be computed as follows: creating a tuple (v) for each computation which is to be converted to a machine instruction by the compiler creating a table (optimally, a hash table) having an entry for all the tuples in the program being compiled; for every Basis element in a tuple being entered in the table a symbolic register uniquely assigned to that tuple is added to the Kill Set for that Basis element. For every non-basis element "n" in the tuple being entered into the table, the uniquely assigned symbolic register for that tuple is added to the Kill Sets for all the Basis elements in whose Kill Sets that non-basis element "n" appears.

Abstract: A mechanism for performing a run-time storage address validity check within one machine cycle. The mechanism, functioning together with an intelligent compiler, eliminates the need for hardware implementation of a storage validity check. More particularly, the mechanism performs its function in one machine cycle in the event that a trap exception does not cause an interrupt. In the rare instance when an interrupt is necessary, a number of machine cycles will be impacted. The mechanism comprises a minimum amount of logic circuitry for determining the trap condition operating in conjunction with conventional, previously existing compare, branch instruction testing, and interrupt generation circuitry.

Abstract: A mechanism including an expanded condition register for use in a reduced instruction set computing system which facilitates the performance of single machine cycle instructions on the system and further provides for the efficient execution of more complex instructions which are not susceptible of being completed in a single machine cycle. More particularly, a mechanism is provided for setting the bits of the expanded condition register whereby a more efficient restart is possible after a machine interrupt and whereby the results of intermediate operations of certain multistep logic and arithmetic operations are maintained in the condition register in order that the cycle time of such multistep operations may be kept to a minimum, and when necessary, may be executed with greater efficiency.

Abstract: A mechanism for performing fast and efficient full shift, merge, insert and bit alignment functions within one operating machine cycle of a host primitive instructions set computing system. In general, the circuitry performs a ring shift under control of a mask. The circuitry further combines essentially parallel rotate and mask and merge functions all executable in one machine cycle. The circuitry further allows the provision of powerful bit, digit, and bit rotate with mask instructions which are particularly useful primitive operations for decimal packing and unpacking functions as well as for implementing floating point preshifting and normalization functions.