Abstract: Methods and apparatus optimized for compiling instructions in a data processor are disclosed. In one aspect, a method of address calculation is disclosed, comprising operating a compiler to generate at least one instruction; canonicalizing the address calculation in a plurality of different approaches: in one exemplary embodiment, the first approach comprises canonicalizing the “regular” 32-bit instruction addressing modes, and the second for the “compressed” 16-bit instruction addressing modes. In another aspect, a plurality of functions (up to and including all available functions) are called indirectly to allow addresses to be placed in a constant pool. Improved methods for instruction selection, register allocation and spilling, and instruction compression are provided. An improved SoC integrated circuit device having an optimized 32-bit/16-bit processor core implementing at least one of the foregoing improvements is also disclosed.

Abstract: An improved method of optimizing the instruction set of a digital processor using code compression. In one embodiment, the method comprises obtaining an assembly language program to be used for the optimization process; calculating the static frequency of each instruction type from the base instruction set; sorting the instruction types by frequency; determining the number and type of instructions necessary for correct program execution; creating a compressed instruction set encoding; re-evaluating the compressed instruction according to the foregoing steps; and generating an instruction set encoding for the compressed instruction set. Improved compressed instruction formats and register structures useful in a processor are also disclosed. A computer program and apparatus for synthesizing logic implementing the aforementioned data cache architecture and pipeline performance enhancements are further disclosed.

Abstract: Methods and apparatus optimized for compiling instructions in a data processor are disclosed. In one aspect, a method of address calculation is disclosed, comprising operating a compiler to generate at least one instruction; canonicalizing the address calculation in a plurality of different approaches: in one exemplary embodiment, the first approach comprises canonicalizing the “regular” 32-bit instruction addressing modes, and the second for the “compressed” 16-bit instruction addressing modes. In another aspect, a plurality of functions (up to and including all available functions) are called indirectly to allow addresses to be placed in a constant pool. Improved methods for instruction selection, register allocation and spilling, and instruction compression are provided. An improved SoC integrated circuit device having an optimized 32-bit/16-bit processor core implementing at least one of the foregoing improvements is also disclosed.

Abstract: Methods and apparatus optimized for compiling instructions in a data processor are disclosed. In one aspect, a method of address calculation is disclosed, comprising operating a compiler to generate at least one instruction; canonicalizing the address calculation in a plurality of different approaches: in one exemplary embodiment, the first approach comprises canonicalizing the “regular” 32-bit instruction addressing modes, and the second for the “compressed” 16-bit instruction addressing modes. In another aspect, a plurality of functions (up to and including all available functions) are called indirectly to allow addresses to be placed in a constant pool. Improved methods for instruction selection, register allocation and spilling, and instruction compression are provided. An improved SoC integrated circuit device having an optimized 32-bit/16-bit processor core implementing at least one of the foregoing improvements is also disclosed.

Abstract: An improved method of optimizing the instruction set of a digital processor using code compression. In one embodiment, the method comprises obtaining an assembly language program to be used for the optimization process; calculating the static frequency of each instruction type from the base instruction set; sorting the instruction types by frequency; determining the number and type of instructions necessary for correct program execution; creating a compressed instruction set encoding; re-evaluating the compressed instruction according to the foregoing steps; and generating an instruction set encoding for the compressed instruction set. Improved compressed instruction formats and register structures useful in a processor are also disclosed. A computer program and apparatus for synthesizing logic implementing the aforementioned data cache architecture and pipeline performance enhancements are further disclosed.

Abstract: An improved method and apparatus for implementing instructions in a pipelined central processing unit (CPU) or user-customizable microprocessor. In a first aspect of the invention, an improved method of controlling branching and the execution of instructions within the pipeline is disclosed. In one embodiment, the method comprises defining three discrete delay slot modes within program jump instructions; these delay slot modes specify the execution of subsequent instructions or the stalling of the pipeline as desired by the programmer. In a second aspect of the invention, a method of synthesizing a processor design incorporating the aforementioned modes is disclosed. Exemplary gate logic synthesized using the aforementioned methods, and a computer system capable of implementing these methods, are also described.

Abstract: An improved method of optimizing the instruction set of a digital processor using code compression. In one embodiment, the method comprises obtaining an assembly language program to be used for the optimization process; calculating the static frequency of each instruction type from the base instruction set; sorting the instruction types by frequency; determining the number and type of instructions necessary for correct program execution; creating a compressed instruction set encoding; re-evaluating the compressed instruction according to the foregoing steps; and generating an instruction set encoding for the compressed instruction set. Improved compressed instruction formats and register structures useful in a processor are also disclosed. A computer program and apparatus for synthesizing logic implementing the aforementioned data cache architecture and pipeline performance enhancements are further disclosed.

Abstract: Digital processor apparatus having an instruction set architecture (ISA) with instruction words of varying length. In the exemplary embodiment, the processor comprises an extended user-configurable RISC processor with four-stage pipeline (fetch, decode, and writeback) and associated logic that is adapted to decode and process both 32-execute, bit and 16-bit instruction words present in a single program, thereby increasing the flexibility of the instruction set, and allowing for greater code compression and reduced memory overhead. Free-form use of the different length instructions is provided with no required mode shift. An improved instruction aligner and code compression architecture is also disclosed.

Abstract: An improved method of optimizing the instruction set of a digital processor using code compression. In one embodiment, the method comprises obtaining an assembly language program to be used for the optimization process; calculating the static frequency of each instruction type from the base instruction set; sorting the instruction types by frequency; determining the number and type of instructions necessary for correct program execution; creating a compressed instruction set encoding; re-evaluating the compressed instruction according to the foregoing steps; and generating an instruction set encoding for the compressed instruction set. Improved compressed instruction formats and register structures useful in a processor are also disclosed. A computer program and apparatus for synthesizing logic implementing the aforementioned data cache architecture and pipeline performance enhancements are further disclosed.