Patents by Inventor Peter West
Peter West has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11662417Abstract: An active marker device, and method of design thereof, for use in a motion tracking system are provided. In one arrangement, the device comprises a mounting body comprising a mounting surface. A plurality of light emitting units are mounted on respective mounting portions of the mounting surface. A control system controls the plurality of light emitting units such that light is emitted simultaneously from a selected subset of light emitting units. A plurality of optical elements are mounted on the mounting surface. Each optical element covers a different one of the light emitting units and is configured so that an inner surface of the optical element is separated from an outer surface of the light emitting unit. Each optical element redirects a portion of light emitted by the light emitting unit covered by the optical element to be more parallel to the mounting portion of the light emitting unit.Type: GrantFiled: August 1, 2019Date of Patent: May 30, 2023Assignee: OXFORD METRICS PLCInventors: Peter West, Miles Beattie, Paul Smyth, Phil Pritchett, José Araujo, David Reynolds
-
Publication number: 20230065066Abstract: In one aspect, a method of fabricating a transistor includes depositing a first epitaxial layer; depositing a second epitaxial layer on the first epitaxial layer; forming a single termination trench in the second epitaxial layer; and filling the termination trench with a dielectric. A depth of the termination trench is greater than 10 microns. In another aspect, a transistor includes a first epitaxial layer; a second epitaxial layer on the first epitaxial layer; and a single termination trench in the second epitaxial layer. The termination trench is greater than 10 microns and is filled with a dielectric.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: Polar Semiconductor, LLCInventors: Noel Hoilien, Peter West, Rajesh Appat
-
Patent number: 11245006Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.Type: GrantFiled: December 23, 2019Date of Patent: February 8, 2022Assignees: Polar Semiconductor, LLC, SANKEN ELECTRIC CO., LTD.Inventors: Dosi Dosev, Don Rankila, Tatsuya Kamimura, Shunsuke Fukunaga, Steven L. Kosier, Peter West
-
Publication number: 20210318405Abstract: An active marker device, and method of design thereof, for use in a motion tracking system are provided. In one arrangement, the device comprises a mounting body comprising a mounting surface. A plurality of light emitting units are mounted on respective mounting portions of the mounting surface. A control system controls the plurality of light emitting units such that light is emitted simultaneously from a selected subset of light emitting units. A plurality of optical elements are mounted on the mounting surface. Each optical element covers a different one of the light emitting units and is configured so that an inner surface of the optical element is separated from an outer surface of the light emitting unit. Each optical element redirects a portion of light emitted by the light emitting unit covered by the optical element to be more parallel to the mounting portion of the light emitting unit.Type: ApplicationFiled: August 1, 2019Publication date: October 14, 2021Applicant: OXFORD METRICS PLCInventors: Peter WEST, Miles BEATTIE, Paul SMYTH, Phil PRITCHETT, José ARAUJO, David Reynolds
-
Patent number: 10896885Abstract: Apparatus and associated methods relate to a bond-pad structure having small pad-substrate capacitance for use in high-voltage MOSFETs. The bond-pad structure includes upper and lower polysilicon plates interposed between a metal bonding pad and an underlying semiconductor substrate. The lower polysilicon plate is encapsulated in dielectric materials, thereby rendering it floating. The upper polysilicon plate is conductively coupled to a source of the high-voltage MOSFET. A perimeter of the metal bonding pad is substantially circumscribed, as viewed from a plan view perspective, by a perimeter of the upper polysilicon plate. A perimeter of the upper polysilicon plate is substantially circumscribed, as viewed from the plan view perspective, by a perimeter of the lower polysilicon plate. In some embodiments, the metal bonding pad is conductively coupled to a gate of the high-voltage MOSFET. The pad-substrate capacitance is advantageously made small by this bond-pad structure.Type: GrantFiled: September 13, 2017Date of Patent: January 19, 2021Assignees: Polar Semiconductor, LLC, Sanken Electric Co., Ltd.Inventors: Peter West, Dosi Dosev, Don Rankila, Tatsuya Kamimura, Steve Kosier
-
Publication number: 20200127092Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.Type: ApplicationFiled: December 23, 2019Publication date: April 23, 2020Applicants: Polar Semiconductor, LLC, SANKEN ELECTRIC CO., LTD.Inventors: Dosi Dosev, Don Rankila, Tatsuya Kamimura, Shunsuke Fukunaga, Steven L. Kosier, Peter West
-
Patent number: 10580861Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.Type: GrantFiled: February 20, 2018Date of Patent: March 3, 2020Assignees: POLAR SEMICONDUCTOR, LLC, SANKEN ELECTRIC CO., LTD.Inventors: Dosi Dosev, Don Rankila, Tatsuya Kamimura, Shunsuke Fukunaga, Steven Kosier, Peter West
-
Publication number: 20190081016Abstract: Apparatus and associated methods relate to a bond-pad structure having small pad-substrate capacitance for use in high-voltage MOSFETs. The bond-pad structure includes upper and lower polysilicon plates interposed between a metal bonding pad and an underlying semiconductor substrate. The lower polysilicon plate is encapsulated in dielectric materials, thereby rendering it floating. The upper polysilicon plate is conductively coupled to a source of the high-voltage MOSFET. A perimeter of the metal bonding pad is substantially circumscribed, as viewed from a plan view perspective, by a perimeter of the upper polysilicon plate. A perimeter of the upper polysilicon plate is substantially circumscribed, as viewed from the plan view perspective, by a perimeter of the lower polysilicon plate. In some embodiments, the metal bonding pad is conductively coupled to a gate of the high-voltage MOSFET. The pad-substrate capacitance is advantageously made small by this bond-pad structure.Type: ApplicationFiled: September 13, 2017Publication date: March 14, 2019Inventors: Peter West, Dosi Dosev, Don Rankila, Tatsuya Kamimura, Steve Kosier
-
Publication number: 20190081147Abstract: Apparatus and associated methods relate to a trench Metal-Oxide-Semiconductor Field-effect Transistor (MOSFET). The trench MOSFET includes a pair of longitudinal trenches formed in a semiconductor die, thereby forming an intervening longitudinal semiconductor pillar therebetween. Each of the pair of trenches has a field plates dielectrically isolated from a conductive gate. Each of the conductive gates is dielectrically isolated from the intervening semiconductor pillar via a gate dielectric. The thickness of the gate dielectric varies along a vertical dimension of the conductive gate, thereby providing a variation in a separation distance between each conductive gate and the intervening semiconductor pillar. The separation distance decreases from a gate/source overlap region to a channel inversion region. Such a varying separation distance can advantageously improve MOSFET operating parameters.Type: ApplicationFiled: September 13, 2017Publication date: March 14, 2019Inventors: Peter West, Dosi Dosev, Don Rankila, Tatsuya Kamimura, Steve Kosier
-
Publication number: 20180175146Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.Type: ApplicationFiled: February 20, 2018Publication date: June 21, 2018Inventors: Dosi Dosev, Don Rankila, Tatsuya Kamimura, Shunsuke Fukunaga, Steven Kosier, Peter West
-
Patent number: 9899343Abstract: Apparatus and associated methods relate to a bonding pad structure for a trench-based semiconductor device. The bonding pad structure reduces a peak magnitude of the electric field between a metal bonding pad and the underlying semiconductor. The bonding pad structure includes a plurality of trenches vertically extending from a top surface of a semiconductor. Each of the plurality of trenches has dielectric sidewalls and a dielectric bottom, the dielectric sidewalls and dielectric bottom electrically isolating a conductive core within each of the trenches from a region of semiconductor outside of and adjacent to each of the plurality of trenches. The bonding pad structure includes a metal bonding pad disposed above the plurality of trenches, the metal bonding pad electrically isolated from the region of semiconductor outside of the trenches. The conductive core can be biased to reduce the magnitude of the field between adjacent trenches.Type: GrantFiled: March 9, 2016Date of Patent: February 20, 2018Assignees: Polar Semiconductor, LLC, SANKEN ELECTRIC CO., LTD.Inventors: Peter West, Steven Kosier, Tatsuya Kamimura, Don Rankila
-
Patent number: 9818828Abstract: Apparatus and associated methods relate to an edge-termination structure surrounding a high-voltage MOSFET for reducing a peak lateral electric field. The edge-termination structure includes a sequence of annular trenches and semiconductor pillars circumscribing the high-voltage MOSFET. Each of the annular trenches is laterally separated from the other annular trenches by one of the semiconductor pillars. Each of the annular trenches has dielectric sidewalls and a dielectric bottom electrically isolating a conductive core within each of the annular trenches from a drain-biased region of the semiconductor pillar outside of and adjacent to the annular trench. The conductive core of the innermost trench is biased, while the conductive cores of one or more outer trenches are floating. In some embodiments, a surface of an inner semiconductor pillar is biased as well. The peak lateral electric field can advantageously be reduced by physical arrangement of trenches and electrical biasing sequence.Type: GrantFiled: March 9, 2016Date of Patent: November 14, 2017Assignees: POLAR SEMICONDUCTOR, LLC, SANKEN ELECTRIC CO., LTD.Inventors: Peter West, Steven Kosier, Tatsuya Kamimura, Don Rankila
-
Publication number: 20170263580Abstract: Apparatus and associated methods relate to a bonding pad structure for a trench-based semiconductor device. The bonding pad structure reduces a peak magnitude of the electric field between a metal bonding pad and the underlying semiconductor. The bonding pad structure includes a plurality of trenches vertically extending from a top surface of a semiconductor. Each of the plurality of trenches has dielectric sidewalls and a dielectric bottom, the dielectric sidewalls and dielectric bottom electrically isolating a conductive core within each of the trenches from a region of semiconductor outside of and adjacent to each of the plurality of trenches. The bonding pad structure includes a metal bonding pad disposed above the plurality of trenches, the metal bonding pad electrically isolated from the region of semiconductor outside of the trenches. The conductive core can be biased to reduce the magnitude of the field between adjacent trenches.Type: ApplicationFiled: March 9, 2016Publication date: September 14, 2017Inventors: Peter West, Steven Kosier, Tatsuya Kamimura, Don Rankila
-
Publication number: 20170263718Abstract: Apparatus and associated methods relate to an edge-termination structure surrounding a high-voltage MOSFET for reducing a peak lateral electric field. The edge-termination structure includes a sequence of annular trenches and semiconductor pillars circumscribing the high-voltage MOSFET. Each of the annular trenches is laterally separated from the other annular trenches by one of the semiconductor pillars. Each of the annular trenches has dielectric sidewalls and a dielectric bottom electrically isolating a conductive core within each of the annular trenches from a drain-biased region of the semiconductor pillar outside of and adjacent to the annular trench. The conductive core of the innermost trench is biased, while the conductive cores of one or more outer trenches are floating. In some embodiments, a surface of an inner semiconductor pillar is biased as well. The peak lateral electric field can advantageously be reduced by physical arrangement of trenches and electrical biasing sequence.Type: ApplicationFiled: March 9, 2016Publication date: September 14, 2017Inventors: Peter West, Steven Kosier, Tatsuya Kamimura, Don Rankila
-
Publication number: 20170194485Abstract: A power metal-oxide semiconductor field-effect transistor (MOSFET) and method of manufacturing thereof, includes a trench, a trench doping and a pillar doping region. The trench is etched into a silicon layer that includes a gate structure disposed therein. The trench doping is implanted in the silicon layer vertically below the trench and has an opposite doping type than the silicon layer. The pillar doping region is implanted in the silicon layer vertically below, and spaced from the trench doping. The pillar doping region has a same doping type as the trench doping.Type: ApplicationFiled: January 6, 2016Publication date: July 6, 2017Inventors: Christopher Smith, Steven Kosier, Peter West
-
Publication number: 20160247879Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern including a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.Type: ApplicationFiled: February 23, 2016Publication date: August 25, 2016Inventors: Dosi Dosev, Don Rankila, Tatsuya Kamimura, Shunsuke Fukunaga, Steven Kosier, Peter West
-
Patent number: 8654612Abstract: The present invention relates to a system and method for detecting bats from a remote location. In one aspect the invention provides a bat detection system comprising an upper detection unit connected to a base computer unit. The upper detection unit can be positioned on a vertical structure, and a second lower detection unit, or additional detection units, can also be positioned on the vertical structure. Each detection unit comprises a housing which is connected to, and contains, an audio detector. The base computer unit is enclosed by a housing and comprises a data processor, a data storage device, and a remote communication interface device. The data processor is operatively connected to the data storage device, remote communication interface device, and the audio detectors of any detection units positioned on the vertical structure. The base computer unit communicates with a remote computer transferring information regarding the bat sounds detected by the detection units.Type: GrantFiled: July 31, 2012Date of Patent: February 18, 2014Assignee: Normandeau Associates, Inc.Inventors: Michael J. Adler, Christian M. Newman, Christine L. Sutter, Carla Ebeling, Chris Ribe, Peter West
-
Patent number: 8379486Abstract: The present invention relates to a system and method for detecting bats from a remote location. In one aspect the invention provides a bat detection system comprising an upper detection unit connected to a base computer unit. The upper detection unit can be positioned on a vertical structure, and a second lower detection unit, or additional detection units, can also be positioned on the vertical structure. Each detection unit comprises a housing which is connected to, and contains, an audio detector. The base computer unit is enclosed by a housing and comprises a data processor, a data storage device, and a remote communication interface device. The data processor is operatively connected to the data storage device, remote communication interface device, and the audio detectors of any detection units positioned on the vertical structure. The base computer unit communicates with a remote computer transferring information regarding the bat sounds detected by the detection units.Type: GrantFiled: June 17, 2009Date of Patent: February 19, 2013Assignee: Normandeau Associates, Inc.Inventors: Michael J. Adler, Christian M. Newman, Christine L. Sutter, Carla Ebeling, Chris Ribe, Peter West
-
Publication number: 20120300589Abstract: The present invention relates to a system and method for detecting bats from a remote location. In one aspect the invention provides a bat detection system comprising an upper detection unit connected to a base computer unit. The upper detection unit can be positioned on a vertical structure, and a second lower detection unit, or additional detection units, can also be positioned on the vertical structure. Each detection unit comprises a housing which is connected to, and contains, an audio detector. The base computer unit is enclosed by a housing and comprises a data processor, a data storage device, and a remote communication interface device. The data processor is operatively connected to the data storage device, remote communication interface device, and the audio detectors of any detection units positioned on the vertical structure. The base computer unit communicates with a remote computer transferring information regarding the bat sounds detected by the detection units.Type: ApplicationFiled: July 31, 2012Publication date: November 29, 2012Applicant: Normandeau Associates, Inc.Inventors: Michael J. Adler, Christian M. Newman, Christine L. Sutter, Carla Ebeling, Chris Ribe, Peter West
-
Patent number: D992729Type: GrantFiled: September 28, 2021Date of Patent: July 18, 2023Assignee: Owen Mumford LimitedInventors: Luke Pennifold, Peter West