Abstract: Leakage current control devices include a circuit having one or more functions in a data path where the functions are executed in a sequence. Each of the functions has power reduction logic to energize each respective function. A leakage control circuit interacts with the power reduction logic, so that the functions are energized or deenergized in a control sequence such that the functions where the data is resident are energized and at least one of the other functions is not energized.

Abstract: An apparatus and method for externally managing data within an asynchronous pipeline. The asynchronous pipeline over which control is sought includes a data path and a control path. In accordance with the method of the present invention, a data tag value is assigned to the data prior to its entry into the asynchronous pipeline. The data tag value is sent into the control path at the same time the data is sent into its data path such that the data tag value passes through the asynchronous pipeline in parallel with the data to which it is assigned. At a given stage within the asynchronous pipeline, the data tag value is compared with a control tag value, and only in response to the data tag value matching the control tag value is the data permitted to pass to the next stage within the asynchronous pipeline.

Abstract: A device for tensioning web, such as a plastics web dispensed from a shuttle in a wrapping machine, is disclosed. The wrapping machine usually includes an endless track positioned about an object to be wrapped and the shuttle travels on the endless track, dispensing the web as it goes. The rate at which web is dispensed varies as the shuttle progresses around the track and is dependent upon the shape of the track and the shape of the object to be wrapped. The web tensioning device attempts to maintain a constant tension in the web and includes a pair of rollers covered with resilient material. The rollers are urged together to form a nip with the resilient covering of the rollers compressed in the nip. The web is fed between the nip of the rollers.

Abstract: A device for tensioning web, such as a plastics web dispensed from a shuttle in a wrapping machine, is disclosed. The wrapping machine usually includes an endless track positioned about an object to be wrapped and the shuttle travels on the endless track, dispensing the web as it goes. The rate at which web is dispensed varies as the shuttle progresses around the track and is dependent upon the shape of the track and the shape of the object to be wrapped. The web tensioning device attempts to maintain a constant tension in the web and includes a pair of rollers covered with resilient material. The rollers are urged together to form a nip with the resilient covering of the rollers compressed in the nip. The web is fed between the nip of the rollers.

Abstract: An apparatus and method for externally managing data within an asynchronous pipeline. The asynchronous pipeline over which control is sought includes a data path and a control path. In accordance with the method of the present invention, a data tag value is assigned to the data prior to its entry into the asynchronous pipeline. The data tag value is sent into the control path at the same time the data is sent into its data path such that the data tag value passes through the asynchronous pipeline in parallel with the data to which it is assigned. At a given stage within the asynchronous pipeline, the data tag value is compared with a control tag value, and only in response to the data tag value matching the control tag value is the data permitted to pass to the next stage within the asynchronous pipeline.

Abstract: An interlocked pipelined CMOS (IPCMOS) family of logic circuits provides extremely high performance pipelined operation and guarantees error free operation where variations in timing are compensated for automatically by the circuits. The IPCMOS logic circuits also provide a standard interface that makes it possible to interface different macro types easily. The IPCMOS logic circuits feature interlocking in both the forward and reverse directions. This “handshaking” guarantees error free timing and makes it possible to eliminate the need for a global clock at the macro level. Timing signals are generated locally at the macro level from the handshaking signals between macros. This makes it possible for the local circuits to deal with global timing variations caused by power supply noise, ACLV, and parameter variations. The macros operate in a pipelined mode with data advancing automatically from macro to macro with the timing controlled by the local handshaking signals.

Abstract: A method of wire routing includes the steps of providing an array of cells on a semiconductor chip, determining a minimum distance location between a first clock point, an second clock point and a drive point for connecting to a connection point in the array of cells, and defining a wire path through an array of blockages disposed in the array of cells from the minimum distance location to the first clock point and from the minimum distance location to the second clock point to create a path for a wire for connecting the first clock point and the second clock point to a connection point such that skew is minimized between the starting clock point and the second clock point from the connection point when a clock signal is provided to the connection point from the drive point.

Abstract: A comparator circuit for comparing two voltage levels in a C-2C A/D and D/A converter, comprising four cross-coupled active devices (FETs) in a latch arrangement whereby an offset voltage is used to compensate for imbalances in the comparator. The comparator includes a first FET having its gate electrode connected to the output of the D/A converter, and a second FET having its gate electrode connected to an analog input voltage. The first and second FETs each have one of their electrodes connected to a common voltage source. A third and a fourth FET have one of their electrodes connected respectively to the other electrode of the first and second FETs at first and second common nodes, respectively. The output of the comparator is provided at one of such first and second common nodes. The first and second nodes are also respectively connected to the gate electrodes of the fourth and third FETs in a cross-coupled arrangement.

Abstract: A C-2C analog-to digital and digital-to-analog converter is described, the C-2C designation referring to the arrangement of capacitance in a capacitor ladder network. The capacitors are formed in a monolithic, multilayer structure which includes a substrate, diffusion regions in the substrate, a polysilicon layer and an aluminum layer wherein the capacitances are formed between the aluminum layer and the polysilicon layer and between the polysilicon layer and the diffusion region, and these capacitances have the ratio of 2C to C respectively. The capacitor ladder network formed in the multilayer structure can be trimmed or adjusted electrically after manufacture to obtain the desired tolerances.