Patents by Inventor Peter William Hughes
Peter William Hughes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7564274Abstract: A system (10,90), apparatus (12,30,40,50,60,70) and method (100) is disclosed for detecting excess current leakage between drain/source of a metal oxide semiconductor (MOS) transistor (36,46) within a complementary MOS (CMOS) environment. A load control (32,42) is arranged as a compliment to the MOS transistor. A comparator (34,44) is electrically connected to the load control and the MOS transistor, and produces an output signal representative of the detection of a current leakage exceeding a threshold. In response to the received output signal indicating an excess current leakage, system voltage/frequency may be adjusted to prevent damage to the CMOS environment.Type: GrantFiled: February 24, 2005Date of Patent: July 21, 2009Assignee: Icera, Inc.Inventor: Peter William Hughes
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Patent number: 7266787Abstract: A method (300) for optimising transistor performance in semiconductor integrated circuits built from standard cells (12), or custom transistor level layout, is disclosed. An active area of NMOS diffusion is extended with a joining area (102) between two adjacent cells (112) having the same net on diffusion at the adjacent edges of each cell. The diffusion area is extended to limit the occurrence of active and nonactive interface to minimise lattice strain effects and improve transistor performance.Type: GrantFiled: February 24, 2005Date of Patent: September 4, 2007Assignee: Icera, Inc.Inventors: Peter William Hughes, Shannon Vance Morton, Trevor Kenneth Monk
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Patent number: 7100138Abstract: A method for designing multi-layer electronic circuits includes defining a plurality of circuit blocks in terms of physical boundaries, the plurality of circuit blocks including a first circuit block with at least one port for connecting to a portion of inter-block routing having conducting material external to the first circuit block. The method further provides protective routing for the at least one port of the first circuit block in a region between the block and the inter-block routing, wherein circuitry within the first circuit connected to the at least one port is not in-circuit with the conducting material of the inter-block routing during processing steps involving the conducting material. The protective routing is a conducting layer which is higher in the multi-layer structure than the highest conducting layer used for routing the net containing the at least one port for inter-block routing.Type: GrantFiled: June 9, 2004Date of Patent: August 29, 2006Assignee: Broadcom CorporationInventors: Neal Fitzhenry, Peter William Hughes, Simon Christopher Dequin Clemow, Paul Andrew Freeman
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Publication number: 20040225991Abstract: A method for designing multi-layer electronic circuits includes defining a plurality of circuit blocks in terms of physical boundaries, the plurality of circuit blocks including a first circuit block with at least one port for connecting to a portion of inter-block routing having conducting material external to the first circuit block. The method further provides protective routing for the at least one port of the first circuit block in a region between the block and the inter-block routing, wherein circuitry within the first circuit connected to the at least one port is not in-circuit with the conducting material of the inter-block routing during processing steps involving the conducting material. The protective routing is a conducting layer which is higher in the multi-layer structure than the highest conducting layer used for routing the net containing the at least one port for inter-block routing.Type: ApplicationFiled: June 9, 2004Publication date: November 11, 2004Applicant: Broadcom CorporationInventors: Neal Fitzhenry, Peter William Hughes, Simon Christopher Dequin Clemow, Paul Andrew Freeman
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Patent number: 6766503Abstract: A method for designing multi-layer electronic circuits includes defining a plurality of circuit blocks in terms of physical boundaries, the plurality of circuit blocks including a first circuit block with at least one port for connecting to a portion of inter-block routing having conducting material external to the first circuit block. The method further provides protective routing for the at least one port of the first circuit block in a region between the block and the inter-block routing, wherein circuitry within the first circuit connected to the at least one port is not in-circuit with the conducting material of the inter-block routing during processing steps involving the conducting material. The protective routing is a conducting layer which is higher in the multi-layer structure than the highest conducting layer used for routing the net containing the at least one port for inter-block routing.Type: GrantFiled: May 31, 2002Date of Patent: July 20, 2004Assignee: Broadcom CorporationInventors: Neal Fitzhenry, Peter William Hughes, Simon Christopher Dequin Clemow, Paul Andrew Freeman
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Publication number: 20020184601Abstract: A method for designing multi-layer electronic circuits includes defining a plurality of circuit blocks in terms of physical boundaries, the plurality of circuit blocks including a first circuit block with at least one port for connecting to a portion of inter-block routing having conducting material external to the first circuit block. The method further provides protective routing for the at least one port of the first circuit block in a region between the block and the inter-block routing, wherein circuitry within the first circuit connected to the at least one port is not in-circuit with the conducting material of the inter-block routing during processing steps involving the conducting material. The protective routing is a conducting layer which is higher in the multi-layer structure than the highest conducting layer used for routing the net containing the at least one port for inter-block routing.Type: ApplicationFiled: May 31, 2002Publication date: December 5, 2002Applicant: Broadcom CorporationInventors: Neal Fitzhenry, Peter William Hughes, Simon Christopher Dequin Clemow, Paul Andrew Freeman
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Patent number: 6072335Abstract: An output current unit comprises a cascode circuit having a first transistor connected between a voltage supply line and complementary outputs. Second and third transistors are controlled by inverter circuitry having parallel conducting paths between an output node and a ground line, the parallel conducting paths having different current carrying capacity with control circuitry to switch the stronger of the current carrying paths.Type: GrantFiled: November 18, 1997Date of Patent: June 6, 2000Assignee: STMicroelectronics LimitedInventor: Peter William Hughes
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Patent number: 5812121Abstract: An output current unit comprises a cascode circuit having a first transistor connected between a voltage supply line and complementary outputs. Second and third transistors are controlled by inverter circuitry having parallel conducting paths between an output node and a ground line, the parallel conducting paths having different current carrying capacity with control circuitry to switch the stronger of the current carrying paths.Type: GrantFiled: March 2, 1995Date of Patent: September 22, 1998Assignee: SGS-Thomson Microelectronics LimitedInventor: Peter William Hughes
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Patent number: D713764Type: GrantFiled: March 28, 2013Date of Patent: September 23, 2014Assignee: GM Global Technology Operations LLCInventors: Richard Fulvio Ferlazzo, Peter William Hughes, Justin James Thompson, Andrew David James Harrison
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Patent number: D777605Type: GrantFiled: August 19, 2015Date of Patent: January 31, 2017Assignee: GM Global Technology Operations LLCInventors: Richard Fulvio Ferlazzo, Peter William Hughes, Justin James Thompson
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Patent number: D811269Type: GrantFiled: March 25, 2016Date of Patent: February 27, 2018Assignee: GM Global Technology Operations LLCInventors: Justin James Thompson, Peter William Hughes
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Patent number: D813098Type: GrantFiled: March 25, 2016Date of Patent: March 20, 2018Assignee: GM Global Technology Operations LLCInventors: Justin James Thompson, Peter William Hughes
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Patent number: D835003Type: GrantFiled: January 4, 2018Date of Patent: December 4, 2018Assignee: GM Global Technology Operations LLCInventors: Justin James Thompson, Peter William Hughes
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Patent number: D843891Type: GrantFiled: January 23, 2018Date of Patent: March 26, 2019Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLCInventors: Justin James Thompson, Peter William Hughes