Abstract: Data latch circuit and method of low power decision feedback equalization (DFE) system is disclosed. In one embodiment, the data latch circuit of the of a decision feedback equalization (DFE) system includes a first parallel n-channel metal-oxide-semiconductor field-effect transistor (NMOS) pair to input a differential input voltage. The data latch circuit also includes a second parallel NMOS pair coupled to the first parallel NMOS pair to input a decision feedback equalization (DFE) voltage. The data latch circuit further includes a cross-coupled PMOS pair to generate a positive feedback to the first parallel NMOS pair and/or the second parallel NMOS pair. In addition, the data latch circuit includes a cross-coupled NMOS pair to escalate the positive feedback. Furthermore the data latch circuit includes a latching circuit to generate a signal data based on the sinking of a current at an input of the latching circuit and/or the positive feedback.

Abstract: Data latch circuit and method of low power decision feedback equalization (DFE) system is disclosed. In one embodiment, the data latch circuit of the of a decision feedback equalization (DFE) system includes a first parallel n-channel metal-oxide-semiconductor field-effect transistor (NMOS) pair to input a differential input voltage. The data latch circuit also includes a second parallel NMOS pair coupled to the first parallel NMOS pair to input a decision feedback equalization (DFE) voltage. The data latch circuit further includes a cross-coupled PMOS pair to generate a positive feedback to the first parallel NMOS pair and/or the second parallel NMOS pair. In addition, the data latch circuit includes a cross-coupled NMOS pair to escalate the positive feedback. Furthermore the data latch circuit includes a latching circuit to generate a signal data based on the sinking of a current at an input of the latching circuit and/or the positive feedback.

Abstract: Low power decision feedback equalization (DFE) through applying DFE data to input data in a data latch is disclosed. In one embodiment, a decision feedback equalization (DFE) system to remove a post cursor intersymbol interference (ISI) through feeding back previous data scaled with adaptive weights to the DFE system, with each slice of the DFE system may include a first set of decision feedback digital to analog converters (DACs) to generate a first DFE data obtained through the feeding back the previous data scaled with the adaptive weights and a first data latch to generate an output data of the each slice through applying the first DFE data to an input data of the each slice in the first data latch to remove a first delay caused by performing the applying the first DFE data to the input data of the each slice outside of the first data latch.

Abstract: An improved method and apparatus for transmitting digital signals in a communications channel by compensating for distortions due to attenuation of high frequency components suffered by the digital signals. In a preferred embodiment, the digital signals are pulses and the compensation is performed at the transmitter without the need for an emphasis driver, by widening the pulses to compensate for the distortion in the channel that results in narrowing of the pulses incurred in the channel. The resulting pulse train is pre-compensated for the distortions caused by the communications channel. The amount of pre-compensation can be determined statically or dynamically.

Abstract: In a high-speed serial link, an eye finder diagnostic circuit has improved performance by being on-chip with the existing capture latch(es) of a receive equalizer. The eye finder circuit employs an additional capture latch with its input tied to the same input node as the existing capture latch(es) of a receive equalizer. The additional capture latch has a clock input and reference voltage input. The clock input is adjusted through a phase interpolator (or variable delay line) while the reference voltage input is adjusted by a voltage generator. A digital post processing circuit then compares the output of the additional capture latch with the output of the other existing capture latch(es), in order to determine the receive eye opening. The horizontal eye opening is measured by changing the phase of the additional capture latch through the phase interpolator, while the vertical eye opening is measured by changing the reference voltage of the voltage generator of the additional capture latch.

Abstract: Low power decision feedback equalization (DFE) through applying DFE data to input data in a data latch is disclosed. In one embodiment, a decision feedback equalization (DFE) system to remove a post cursor intersymbol interference (ISI) through feeding back previous data scaled with adaptive weights to the DFE system, with each slice of the DFE system may include a first set of decision feedback digital to analog converters (DACs) to generate a first DFE data obtained through the feeding back the previous data scaled with the adaptive weights and a first data latch to generate an output data of the each slice through applying the first DFE data to an input data of the each slice in the first data latch to remove a first delay caused by performing the applying the first DFE data to the input data of the each slice outside of the first data latch.

Abstract: An improved method and apparatus for transmitting digital signals in a communications channel by compensating for distortions due to attenuation of high frequency components suffered by the digital signals. In a preferred embodiment, the digital signals are pulses and the compensation is performed at the transmitter without the need for an emphasis driver, by widening the pulses to compensate for the distortion in the channel that results in narrowing of the pulses incurred in the channel. The resulting pulse train is pre-compensated for the distortions caused by the communications channel. The amount of pre-compensation can be determined statically or dynamically.

Abstract: In a high-speed serial link, an eye finder diagnostic circuit has improved performance by being on-chip with the existing capture latch(es) of a receive equalizer. The eye finder circuit employs an additional capture latch with its input tied to the same input node as the existing capture latch(es) of a receive equalizer. The additional capture latch has a clock input and reference voltage input. The clock input is adjusted through a phase interpolator (or variable delay line) while the reference voltage input is adjusted by a voltage generator. A digital post processing circuit then compares the output of the additional capture latch with the output of the other existing capture latch(es), in order to determine the receive eye opening. The horizontal eye opening is measured by changing the phase of the additional capture latch through the phase interpolator, while the vertical eye opening is measured by changing the reference voltage of the voltage generator of the additional capture latch.

Abstract: A polyphase amplitude detector for detecting the amplitude of a polyphase signal. The polyphase amplitude detector includes means for generating differential pair signals. The differential pair signals are buffered and amplified and then AC coupled to the amplitude detector. The amplitude detector detects the amplitude of each phase of the polyphase signal and generates output signals which are used to control the amplitude of the polyphase signal.