Abstract: A high voltage input circuit includes a triple-well NMOS for reducing the voltage stress across its drain junction for preventing it from breakdown. The triple-well NMOS is fabricated in a P-well formed in a deep N-well on a P-substrate. The P-well is coupled to a power supply voltage by a P-well voltage control device to reduce the voltage difference across the drain junction. A low voltage signal input circuit portion is also added to the high voltage input circuit to allow a high voltage input pin to receive other signal and reduce the total pin count of an integrated circuit. A dual-input buffer such as NAND gate instead of an inverter is used in the low voltage signal input circuit for reducing the voltage stress to the devices in the low voltage signal input circuit.

Abstract: In this invention external high voltages are connected to a chip containing a flash memory that are connected to selected cells to be erased. Internal pump circuits contained on the chip are turned off while the external voltages are used. The external voltages, a high negative voltage and a high positive voltage, are connected to gates and sources respectively of selected cells to be erased by a voltage control module. The external voltages are used during manufacture during program/erase operations to perform the erase function efficiently. The internal high voltage pump circuits are used to erase flash memory cells after being assembled on a circuit board by a user. Two level shifter circuits are disclosed that form a part of the voltage control module. The level shifter circuits apply voltages to the flash memory cells and provide voltages that select and deselect the cells for erasure.

Abstract: In this invention external high voltages are connected to a chip containing a flash memory that are connected to selected cells to be erased. Internal pump circuits contained on the chip are turned off while the external voltages are used. The external voltages, a high negative voltage and a high positive voltage, are connected to gates and sources respectively of selected cells to be erased by a voltage control module. The external voltages are used during manufacture during program/erase operations to perform the erase function efficiently. The internal high voltage pump circuits are used to erase flash memory cells after being assembled on a circuit board by a user. Two level shifter circuits are disclosed that form a part of the voltage control module. The level shifter circuits apply voltages to the flash memory cells and provide voltages that select and deselect the cells for erasure.

Abstract: Bias conditions for improving the efficiency of repairing, programming and erasing the threshold voltages of non-volatile memory devices. A positive voltage is applied to the source region of a non-volatile memory cell. The control gate of the memory cell is applied with another positive voltage higher the voltage at the source region. The difference between the two voltages is proportional to the desired final threshold voltage. The drain region can be applied with a positive voltage directly from the power supply of the memory device. A negative voltage is applied to the bulk of the memory device so that a large electric field across the control gate and the bulk can induce hot-electron injection. By selecting the proper voltage level at the control gate, the method can be used for the repair, program or erase operation of memory devices.

Abstract: In this invention a reverse split gate device is described for creating a flash memory that avoids both programming and erase disturb conditions. The cell is designed so that the stacked gate is associated with the source and the enhancement gate is associated with the drain. This is the reverse of a conventional spit gate design and allows the drain to buffer the stacked gate from bit lines of a flash memory array. The source line now key to both program and erase operations is laid out in rows where two adjacent rows of cells share the same source line. The source line can be segmented to prevent the entire length of the pair of rows from being erased. The cell is programmed by flowing current backwards in the channel and injecting electrons in to the floating gate from an impact ionization that occurs near the source. Erasure is accomplished by Fowler-Nordheim tunneling from the floating gate to the source caused by a potential between the source and the enhancement gate.

Abstract: A flash memory device having a low threshold voltage distribution is disclosed. The threshold voltage in a program state of a flash memory cell is defined to be near or slightly greater than approximately 3.0 volts. The threshold voltage in an erased state is defined to be less than 0.7 volts or at ground level. The low threshold voltage distribution makes it possible to use a low voltage around 3.0 volts for the gate of the memory cell in a read operation. The UV erased threshold is raised to near the threshold voltage of a program state to avoid data retention problem.

Abstract: New bias conditions for flash memory cells and X-decoder circuits for providing the bias conditions. In an erasing operation, a positive high voltage is provided to the bulk and a negative high voltage is provided to the control gate for establishing a sufficient electric field to induce electron tunneling effect. In an operation for repairing a cell's threshold voltage, the biased voltages are reversed. A first X-decoder circuit structure is presented for supplying positive and negative high voltages to the memory cells for block erasing or repairing. The first X-decoder circuit structure has a plurality of X-decoder blocks each being constructed in a separated X-decoder well, and the memory cells are fabricated in a separate common array well. A second X-decoder circuit structure is presented to provide an appropriate bias condition for erasing or repairing a small sector of word lines. For the second X-decoder circuit structure, each memory block is fabricated in a separated array well.

Abstract: Charge pump circuits for stepping up high voltages for flash memory array are disclosed. A first circuit comprises a plurality of series-coupled charge pumps having pump capacitors connected to each pump stage. A first group of charge pumps of the pump circuit are AC coupled through pump capacitors to two non-overlapping pulse trains. To reduce the high voltage that a pump capacitor has to withstand, each pump capacitor after the first group is connected to an earlier pump stage instead of the non-overlapping pulse trains. Therefore, the charge pump circuit can output voltage higher than the breakdown voltage of the pump capacitors. A second circuit comprising a configurable charge pump circuit is also presented.

Abstract: A flash memory circuit includes a word line decoder with even and odd word line latches and a source line decoder with a source line latch. The word line decoders and the source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminate over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that may be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments and having segmented source lines controlled by source segment control lines and transistors, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing.

Abstract: Flash memory circuits provide sector protection or file protection with protection attribute status bits held in a flash memory array. The sector protection protects memory data based on the physical location of the data. The flash memory array is divided into a number of memory sectors. Each memory sector can be protected independently. The size of the memory sector is flexible and may be as large as the whole memory array or as small as a single bit group. Each memory sector has protection bits stored in a protection bit array for indicating the protection state of the sector. A parallel protection structure providing both sector protection and block protection is also included. The parallel protection allows small size data protection as well as large size block protection. File protection protects memory data on a file basis regardless of the physical location of the data. Each file has protection bits stored in an attribute memory for indicating the protection state of the file.

Abstract: A flash memory circuit having a word line decoder with even and odd word line latches and a source line decoder with a source line latch is disclosed. The word line decoders and source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminate over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that can be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing.

Abstract: A flash memory circuit having a word line decoder with even and odd word line latches and a source line decoder with a source line latch is disclosed. The word line decoders and source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminates over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that can be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing.