Abstract: An exhaust muffler for an internal combustion engine includes a housing. A plurality of partitions are disposed within the housing, defining a plurality of chambers. An inlet pipe and an outlet pipe are also disposed within the housing and both the inlet and outlet pipes include a perforated region. The perforated region permits fluid communication between the inlet pipe, outlet pipe and the plurality of chambers. To attenuate engine noise, the perforated regions of the inlet and outlet pipes are positioned at opposite ends of the housing, forcing the exhaust gas to pass through each of the plurality of partitions and chambers, thereby damping the sound waves with minimum effect on engine back pressure levels. Alternatively, the perforated regions of the inlet and outlet pipes may be aligned in a cross-flow chamber.

Abstract: An exhaust muffler for an internal combustion engine includes a housing. A plurality of partitions are disposed within the housing, defining a plurality of chambers. An inlet pipe and an outlet pipe are also disposed within the housing and both the inlet and outlet pipes include a perforated region. The perforated region permits fluid communication between the inlet pipe, outlet pipe and the plurality of chambers. To attenuate engine noise, the perforated regions of the inlet and outlet pipes are positioned at opposite ends of the housing, forcing the exhaust gas to pass through each of the plurality of partitions and chambers, thereby damping the sound waves with minimum effect on engine back pressure levels. Alternatively, the perforated regions of the inlet and outlet pipes may be aligned in a cross-flow chamber.

Abstract: In one embodiment, the methods and apparatuses detect a network bandwidth; detect a sequence of frames; determine a motion based on the sequence of frames; set a target bit rate for the sequence of frames based on the network bandwidth; and set a frame rate for the sequence of frames based on the motion of the sequence of frames, wherein the target bit rate and the frame rate are utilized to process the sequence of frames.

Abstract: In one embodiment, the methods and apparatuses detect a current macroblock and an adjacent macroblock within the scene; detect a mode of the adjacent macroblock; and select a skip mode as a mode for the current macroblock based on the mode of the adjacent macroblock.

Abstract: In a passive liquid crystal display, frames or fields are displayed for different time periods to achieve gray scale. The voltage pulses applied to the column electrodes have substantially constant values during row scanning periods or field scanning periods to reduce power consumption. The lines of the display may be divided into odd and even fields in an interlaced configuration to suppress flicker and to further reduce power consumption by reducing frame rate.

Abstract: In one embodiment, the methods and apparatuses detect a current macroblock and an adjacent macroblock within the scene; detect a mode of the adjacent macroblock; and select a skip mode as a mode for the current macroblock based on the mode of the adjacent macroblock.

Abstract: In one embodiment, the methods and apparatuses detect a network bandwidth; detect a sequence of frames; determine a motion based on the sequence of frames; set a target bit rate for the sequence of frames based on the network bandwidth; and set a frame rate for the sequence of frames based on the motion of the sequence of frames, wherein the target bit rate and the frame rate are utilized to process the sequence of frames.

Abstract: A capacitor divider comprising a plurality of capacitors is used for driving liquid crystal displays. The use of capacitor dividers reduces power consumption, which would be desirable for portable devices. Power consumption is reduced in some embodiments where no static current would flow in the divider.

Abstract: A low DC power rail-to-rail buffer amplifier is suitable for liquid crystal display application. The buffer amplifier comprises: a dc bias stage, a pair of complementary differential amplifiers, a second stage amplifier, and output stage. The dc bias stage is used for the dc bias of the differential amplifiers and the second stage to obtain a rail-to-rail operation. This buffer amplifier can be operated in the power supply ranges of 5.5 V to the breakdown voltage. Simulated results show that the circuit draws only 5.3 ?A static current.

Abstract: Two separate power supplies are employed to generate electrical potentials for driving row and column electrodes of LCDs. One or more energy storage devices are preferably used together with the two power supplies for generating such potentials. In the first phase, the energy storage devices are charged and in the second phase, such devices and the power supplies are employed to generate the appropriate potentials for driving the row and column electrodes. Such schemes permit the column electrodes to be driven through a voltage range much smaller than the convention IAPT driving schemes and vastly reduces the power consumption by the driver. The total voltage dynamic range experienced by the driver circuit is comparable to the IAPT driving scheme.

Abstract: Two separate power supplies are employed to generate electrical potentials for driving row and column electrodes of LCDs. One or more energy storage devices are preferably used together with the two power supplies for generating such potentials. In the first phase, the energy storage devices are charged and in the second phase, such devices and the power supplies are employed to generate the appropriate potentials for driving the row and column electrodes. Such schemes permit the column electrodes to be driven through a voltage range much smaller than the convention IAPT driving schemes and vastly reduces the power consumption by the driver. The total voltage dynamic range experienced by the driver circuit is comparable to the IAPT driving scheme.

Abstract: An image sensor includes an imaging region having a 1.25 or 1.5 transistor per pixel ratio. The 1.5 transistor/pixel imaging region includes two pairs of pixels, the first pair arranged in parallel and the second pair arranged in an offset arrangement. The pixels share a read out and reset transistor. The 1.25 transistor/pixel imaging region includes 2 blocks of 4 pixels arranged in parallel that share a read out and reset transistor.

Abstract: In a passive liquid crystal display, frames or fields are displayed for different time periods to achieve gray scale. The voltage pulses applied to the column electrodes have substantially constant values during row scanning periods or field scanning periods to reduce power consumption. The lines of the display may be divided into odd and even fields in an interlaced configuration to suppress flicker and to further reduce power consumption by reducing frame rate.

Abstract: Two separate power supplies are employed to generate electrical potentials for driving row and column electrodes of LCDs. One or more energy storage devices are preferably used together with the two power supplies for generating such potentials. In the first phase, the energy storage devices are charged and in the second phase, such devices and the power supplies are employed to generate the appropriate potentials for driving the row and column electrodes. Such schemes permit the column electrodes to be driven through a voltage range much smaller than the convention IAPT driving schemes and vastly reduces the power consumption by the driver. The total voltage dynamic range experienced by the driver circuit is comparable to the IAPT driving scheme.