Patents by Inventor Peter Y. T. Hsu

Peter Y. T. Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for preventing multi-level cache system deadlock in a multi-processor system
    Patent number: 5632025
    Abstract: A method for preventing deadlock due to the need for data exclusivity when performing forced atomic instructions in a multi-level cache in a multi-processor system. The system determines whether an aligned multi-byte word in which the data of a forced atomic instruction, such as an integer store operation, is exclusive in a first level cache. If so, the forced atomic instruction is allowed to enter a second level cache pipeline. If not, the forced atomic instruction is prevented from entering the second level cache pipeline and a cache miss and fill operation is initiated to cause the aligned word to be exclusive in the first level cache.
    Type: Grant
    Filed: August 14, 1996
    Date of Patent: May 20, 1997
    Assignee: Silicon Graphics, Inc.
    Inventors: Joseph P. Bratt, John Brennan, Peter Y. T. Hsu, William A. Huffman, Joseph T. Scanlon, Steve Ciavaglia