Patents by Inventor Peter Y. YU

Peter Y. YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hetero-epitaxial output device array with serial connections
    Patent number: 11056560
    Abstract: A GaN-on-Si output transistor array comprises a plurality of small monolithic output transistors. Multiple pieces of the small monolithic GaN films are grown epitaxially on the silicon substrate. Each small monolithic output transistor is formed in a respective small monolithic GaN film. The normal transistors are connected in serial, while the defective transistors are not connected.
    Type: Grant
    Filed: May 25, 2020
    Date of Patent: July 6, 2021
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventors: Guobiao Zhang, Peter Y. Yu
  • Hetero-Epitaxial Output Device Array with Serial Connections
    Publication number: 20200287001
    Abstract: A GaN-on-Si output transistor array comprises a plurality of small monolithic output transistors. Multiple pieces of the small monolithic GaN films are grown epitaxially on the silicon substrate. Each small monolithic output transistor is formed in a respective small monolithic GaN film. The normal transistors are connected in serial, while the defective transistors are not connected.
    Type: Application
    Filed: May 25, 2020
    Publication date: September 10, 2020
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventors: Guobiao ZHANG, Peter Y. YU
  • Hetero-epitaxial output device array
    Patent number: 10707308
    Abstract: A GaN-on-Si output transistor array comprises a plurality of small monolithic output transistors. The substrate surface has multiple grids, upon which multiple pieces of the small monolithic GaN films are grown epitaxially on the silicon substrate. Each small monolithic output transistor is formed in a respective small monolithic GaN film. By disabling defective transistors, the overall yield/reliability is improved.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: July 7, 2020
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventors: Guobiao Zhang, Peter Y. Yu
  • Hetero-Epitaxial Output Device Array
    Publication number: 20190198624
    Abstract: A GaN-on-Si output transistor array comprises a plurality of small monolithic output transistors. The substrate surface has multiple grids, upon which multiple pieces of the small monolithic GaN films are grown epitaxially on the silicon substrate. Each small monolithic output transistor is formed in a respective small monolithic GaN film. By disabling defective transistors, the overall yield/reliability is improved.
    Type: Application
    Filed: December 24, 2018
    Publication date: June 27, 2019
    Applicant: HangZhou HaiCun Information Technology Co., Ltd.
    Inventors: Guobiao ZHANG, Peter Y. YU