Patents by Inventor Peter Yan

Peter Yan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11551851
    Abstract: A module substrate antenna includes: a laminate in which a plurality of ferrite layers are stacked; antennal coils provided on surfaces of the respective ferrite layers; a connection pad connected to an external circuit; and a lead wire provided between the laminate and the connection pad. In the laminate, the antenna coils are two types of the antenna coils, and the two types of the antenna coils are alternately stacked.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: January 10, 2023
    Assignees: TODA KOGYO CORP., SECURITAG ASSEMBLY GROUP CO., LTD.
    Inventors: Jun Koujima, Mark Chang, Yoshiteru Kouno, Peter Yan
  • Publication number: 20220211318
    Abstract: Systems, methods and programs for processing EEG data for display and/or automatically detecting a seizure in a patient based on one or more spectrograms created from the EEG data. EEG data from a patient may be paired into channels based on electrode locations. Spectrograms are generated from EEG data from channels, respectively. The spectrograms of different channels are grouped and a median power spectrogram (MPS) is calculated for the group. The MPS may be used to automatically determine whether the patient had a seizure by applying a machined learned model (ML) model. The ML model is trained and tested using historical EEG data from a plurality of patients. The MPS or a relationship between a plurality of MPS of different groups may be displayed on a bedside monitor in real-time for viewing by a bedside clinician.
    Type: Application
    Filed: April 29, 2020
    Publication date: July 7, 2022
    Applicant: CORNELL UNIVERSITY
    Inventors: Peter YAN, Zachary GRINSPAN
  • Patent number: 11334355
    Abstract: Technology for providing data to a processing unit is disclosed. A computer processor may be divided into a master processing unit and consumer processing units. The master processing unit at least partially decodes a machine instruction and determines whether data is needed to execute the machine instruction. The master processing unit sends a request to memory for the data. The request may indicate that the data is to be sent from the memory to a consumer processing unit. The data sent by the memory in response to the request may be stored in local read storage that is close to the consumer processing unit for fast access. The master processing unit may also provide the machine instruction to the consumer processing unit. The consumer processing unit may access the data from the local read storage and execute the machine instruction based on the accessed data.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: May 17, 2022
    Assignee: Futurewei Technologies, Inc.
    Inventors: Alan Gatherer, Sushma Wokhlu, Peter Yan, Ywhpyng Harn, Ashish Rai Shrivastava, Tong Sun, Lee Dobson McFearin
  • Publication number: 20190304662
    Abstract: A module substrate antenna includes: a laminate in which a plurality of ferrite layers are stacked; antennal coils provided on surfaces of the respective ferrite layers; a connection pad connected to an external circuit; and a lead wire provided between the laminate and the connection pad. In the laminate, the antenna coils are two types of the antenna coils, and the two types of the antenna coils are alternately stacked.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 3, 2019
    Inventors: Jun KOUJIMA, Mark CHANG, Yoshiteru KOUNO, Peter Yan
  • Patent number: 10387355
    Abstract: Disclosed is method for operating an interposer that includes assigning a binary port weight to a plurality of input ports of the interposer. The sum of all of the port weights is less than or equal to a number of traversals available to the interposer in a cycle. A traversal counter is set zero at the beginning of each cycle. The output of the traversal counter is a binary number of m bits. A mask is generated when a bit of the traversal counter transitions from a zero to a one. The mask is generated having the m?k+1 bit of the mask equal to one and all other bits of the mask equal to zero. Data is transmitted from each port when both the binary port weight and the mask have a one in the same bit position.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: August 20, 2019
    Assignee: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Peter Yan, Alex Elisa Chandra, Lee Dobson McFearin, Fang Yu, Alan Gatherer
  • Patent number: 10289598
    Abstract: A described embodiment of the present invention includes a network having a first, second and third plurality of routers connected to a plurality of endpoints. At least one of the first plurality of routers includes a plurality of interposers having a number of queues. The at least one of the first plurality of routers has a demultiplexer for each interposer configured to receive multiplexed data from the interposer and provide demultiplexed data on to a plurality of second queues corresponding to the first queues of the number of queues. The at least one of the first plurality of routers also includes a number multiplexers, each of the number multiplexers having inputs configured to receive data from the number of queues.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: May 14, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: Peter Yan, Alex Elisa Chandra, YwhPyng Harn, Xiaotao Chen, Alan Gatherer, Fang Yu, Xingfeng Chen, Zhuolei Wang, Yang Zhou
  • Patent number: 10185606
    Abstract: Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: January 22, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: Peter Yan, Alan Gatherer, Alex Elisa Chandra, Lee Dobson Mcfearin, Mark Brown, Debashis Bhattacharya, Fang Yu, Xingfeng Chen, Yan Bei, Ke Ning, Chushun Huang, Tong Sun, Xiaotao Chen
  • Publication number: 20180321939
    Abstract: Technology for providing data to a processing unit is disclosed. A computer processor may be divided into a master processing unit and consumer processing units. The master processing unit at least partially decodes a machine instruction and determines whether data is needed to execute the machine instruction. The master processing unit sends a request to memory for the data. The request may indicate that the data is to be sent from the memory to a consumer processing unit. The data sent by the memory in response to the request may be stored in local read storage that is close to the consumer processing unit for fast access. The master processing unit may also provide the machine instruction to the consumer processing unit. The consumer processing unit may access the data from the local read storage and execute the machine instruction based on the accessed data.
    Type: Application
    Filed: May 4, 2017
    Publication date: November 8, 2018
    Applicant: Futurewei Technologies, Inc.
    Inventors: Alan Gatherer, Sushma Wokhlu, Peter Yan, Ywhpyng Harn, Ashish Rai Shrivastava, Tong Sun, Lee Dobson McFearin
  • Publication number: 20170293586
    Abstract: Disclosed is method for operating an interposer that includes assigning a binary port weight to a plurality of input ports of the interposer. The sum of all of the port weights is less than or equal to a number of traversals available to the interposer in a cycle. A traversal counter is set zero at the beginning of each cycle. The output of the traversal counter is a binary number of m bits. A mask is generated when a bit of the traversal counter transitions from a zero to a one. The mask is generated having the m?k+1 bit of the mask equal to one and all other bits of the mask equal to zero. Data is transmitted from each port when both the binary port weight and the mask have a one in the same bit position.
    Type: Application
    Filed: April 12, 2016
    Publication date: October 12, 2017
    Inventors: Peter Yan, Alex Elisa Chandra, Lee Dobson McFearin, Fang Yu, Alan Gatherer
  • Publication number: 20170293512
    Abstract: Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.
    Type: Application
    Filed: April 12, 2016
    Publication date: October 12, 2017
    Inventors: Peter Yan, Alan Gatherer, Alex Elisa Chandra, Lee Dobson Mcfearin, Mark Brown, Debashis Bhattacharya, Fang Yu, Xingfeng Chen, Yan Bei, Ke Ning, Chushun Huang, Tong Sun, Xiaotao Chen
  • Publication number: 20170293587
    Abstract: A described embodiment of the present invention includes a network having a first, second an d third plurality of routers connected to a plurality of endpoints. At least one of the first plurality of routers includes a plurality of interposers having a number of queues. The at least one of the first plurality of routers has a demultiplexer for each interposer configured to receive multiplexed data from the interposer and provide demultiplexed data on to a plurality of second queues corresponding to the first queues of the number of queues. The at least one of the first plurality of routers also includes a number multiplexers, each of the number multiplexers having inputs configured to receive data from the number of queues.
    Type: Application
    Filed: April 12, 2016
    Publication date: October 12, 2017
    Inventors: Peter Yan, Alex Elisa Chandra, YwhPyng Harn, Xiaotao Chen, Alan Gatherer, Fang Yu, Xingfeng Chen, Zhuolei Wang, Yang Zhou
  • Patent number: 9448617
    Abstract: System and method embodiments are provided for messaging-based System-on-a-chip (SoC) power gating. The embodiments enable fine granularity SoC power gating without introducing significant latency and substantially maximizes SoC power reduction. In an embodiment, a method in a first SoC resource for messaging-based power gating includes receiving at the first SoC resource a wakeup notification message (WNM) from a second SoC resource, wherein the WNM comprises a time at which a result message from the second SoC resource is expected to arrive at the first SoC resource; determining with the first SoC resource a wake-up time according to the time at which the result message from the second SoC resource is expected to arrive at the first SoC resource; setting a wake-up time timer to expire at the wake-up time; and waking up the first SoC resource when the wake-up time timer expires when the first SoC resource is asleep.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: September 20, 2016
    Assignee: Futurewei Technologies, Inc.
    Inventors: Mark Brown, Mehran Bagheri, Peter Yan, Alan Gatherer
  • Publication number: 20150261290
    Abstract: System and method embodiments are provided for messaging-based System-on-a-chip (SoC) power gating. The embodiments enable fine granularity SoC power gating without introducing significant latency and substantially maximizes SoC power reduction. In an embodiment, a method in a first SoC resource for messaging-based power gating includes receiving at the first SoC resource a wakeup notification message (WNM) from a second SoC resource, wherein the WNM comprises a time at which a result message from the second SoC resource is expected to arrive at the first SoC resource; determining with the first SoC resource a wake-up time according to the time at which the result message from the second SoC resource is expected to arrive at the first SoC resource; setting a wake-up time timer to expire at the wake-up time; and waking up the first SoC resource when the wake-up time timer expires when the first SoC resource is asleep.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 17, 2015
    Applicant: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Mark Brown, Mehran Bagheri, Peter Yan, Alan Gatherer
  • Patent number: 8215791
    Abstract: An illuminating headlamp consisting of a headband and at least one optical device providing illumination at a known distance from said optical device attached to said headband. Each optical device consists of a housing having an open first end and an open second end. There is a light emitting device attached to a mounting which is attached to the second end causing said light emitting device to be orientated at a known angle to an axis of said housing. At least one optically transparent lens is incorporated into said first end, and a means for adjusting said optically transparent lens in order to cause a focal point of the lens to be positioned behind said light emitting device, wherein a zone of substantially uniform illumination is projected at said known distance.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: July 10, 2012
    Assignee: Designs for Vision, Inc.
    Inventors: Richard E. Feinbloom, Kenneth Braganca, Peter Yan
  • Patent number: 7997759
    Abstract: Disclosed is an illumination device for projecting a substantially uniform light at a remote distance.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: August 16, 2011
    Assignee: Designs For Vision, Inc.
    Inventors: Richard E Feinbloom, Kenneth Braganca, Peter Yan, Michael Botta
  • Patent number: 7980729
    Abstract: Disclosed is an illumination device for projecting a substantially uniform light at a remote distance.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: July 19, 2011
    Assignee: Designs for Vision, Inc.
    Inventors: Richard E. Feinbloom, Kenneth Braganca, Peter Yan, Michael Botta
  • Patent number: 7883233
    Abstract: An assembly for providing illumination to a selected incident area includes a support; a first illumination device coupled to the support, the first illumination device including a first light emitting device and a first lens positioned for focusing light emitted by said first light emitting device; a second illumination device coupled to the support, the second illumination device including a second light emitting device and a second lens positioned for focusing light emitted by said second light emitting device; the first and second lenses projecting defocused images of the respective first and second light emitting devices to the selected incident area.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: February 8, 2011
    Assignee: Designs for Vision, Inc.
    Inventors: Richard Feinbloom, Kenneth Braganca, Peter Yan
  • Patent number: D874463
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: February 4, 2020
    Assignees: TODA KOGYO CORP., SECURITAG ASSEMBLY GROUP CO., LTD.
    Inventors: Jun Koujima, Mark Chang, Yoshiteru Kouno, Peter Yan
  • Patent number: D890007
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: July 14, 2020
    Assignees: TODA KOGYO CORP., SECURITAG ASSEMBLY GROUP CO., LTD.
    Inventors: Jun Koujima, Mark Chang, Yoshiteru Kouno, Peter Yan
  • Patent number: D894773
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: September 1, 2020
    Assignees: TODA KOGYO CORP., SECURITAG ASSEMBLY GROUP CO., LTD.
    Inventors: Jun Koujima, Mark Chang, Yoshiteru Kouno, Peter Yan