Patents by Inventor Peter Yan

Peter Yan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210282886
    Abstract: A system for planning and performing a repeat interventional procedure is provided which includes a registration device and an image generation device which map current targets in a reference image for a first interventional procedure to at least one guidance image acquired from a different imaging modality. Biopsy locations are recorded to the guidance images during the first interventional procedure and the biopsy locations are mapped to the reference image to provide a planning image for use in a subsequent interventional procedure on the patient. In a subsequent interventional procedure, the prior planning image (124) may be registered to a current reference image and the prior biopsy locations and prior and current targets are mapped to a guidance image acquired from a different imaging modality. Biopsy locations are then mapped to the guidance image and mapped back to the current reference image.
    Type: Application
    Filed: May 25, 2021
    Publication date: September 16, 2021
    Inventors: JOCHEN KRUECKER, PINGKUN YAN, AMIR MOHAMMAD TAHMASEBI MARAGHOOSH, PETER A PINTO, BRADFORD JOHNS WOOD
  • Publication number: 20200292539
    Abstract: A system including a sample receptacle configured to receive a test sample and a test strip coupled to the sample receptacle is provided. The test strip configured to generate a signal based on a concentration of a target analyte in the test sample. The system also includes a detector to generate a transduced signal based on the signal and a computer to receive a transduced signal. The computer further determines the concentration of the target analyte in the test sample. For this, the computer retrieves the transduced signal from the detector at multiple time points to determine a signal rate based on a signal value for the time points, and to determine the concentration of the target analyte based on the signal rate and a model. A method and a non-transitory, computer-readable medium storing instructions to use the above system are also provided.
    Type: Application
    Filed: March 12, 2020
    Publication date: September 17, 2020
    Inventors: Peter Yan-Guo REN, Stewart HOELSCHER, Cristian ALBERTO, Stephanie PINEDO, Jason MCCLURE, Dipesh Jaiswal
  • Publication number: 20200116720
    Abstract: An enzymatic extraction agent, as well as methods, compositions and kits for detecting Group A streptococcus in a biological sample, which involve the enzymatic agent, are described.
    Type: Application
    Filed: October 11, 2019
    Publication date: April 16, 2020
    Inventors: Peter Yan-Guo Ren, Stewart Hoelscher, Cristian Alberto, Stephanie Pinedo, Jason McClure, Hyunjin Kim
  • Publication number: 20190304662
    Abstract: A module substrate antenna includes: a laminate in which a plurality of ferrite layers are stacked; antennal coils provided on surfaces of the respective ferrite layers; a connection pad connected to an external circuit; and a lead wire provided between the laminate and the connection pad. In the laminate, the antenna coils are two types of the antenna coils, and the two types of the antenna coils are alternately stacked.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 3, 2019
    Inventors: Jun KOUJIMA, Mark CHANG, Yoshiteru KOUNO, Peter Yan
  • Patent number: 10387355
    Abstract: Disclosed is method for operating an interposer that includes assigning a binary port weight to a plurality of input ports of the interposer. The sum of all of the port weights is less than or equal to a number of traversals available to the interposer in a cycle. A traversal counter is set zero at the beginning of each cycle. The output of the traversal counter is a binary number of m bits. A mask is generated when a bit of the traversal counter transitions from a zero to a one. The mask is generated having the m?k+1 bit of the mask equal to one and all other bits of the mask equal to zero. Data is transmitted from each port when both the binary port weight and the mask have a one in the same bit position.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: August 20, 2019
    Assignee: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Peter Yan, Alex Elisa Chandra, Lee Dobson McFearin, Fang Yu, Alan Gatherer
  • Patent number: 10289598
    Abstract: A described embodiment of the present invention includes a network having a first, second and third plurality of routers connected to a plurality of endpoints. At least one of the first plurality of routers includes a plurality of interposers having a number of queues. The at least one of the first plurality of routers has a demultiplexer for each interposer configured to receive multiplexed data from the interposer and provide demultiplexed data on to a plurality of second queues corresponding to the first queues of the number of queues. The at least one of the first plurality of routers also includes a number multiplexers, each of the number multiplexers having inputs configured to receive data from the number of queues.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: May 14, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: Peter Yan, Alex Elisa Chandra, YwhPyng Harn, Xiaotao Chen, Alan Gatherer, Fang Yu, Xingfeng Chen, Zhuolei Wang, Yang Zhou
  • Publication number: 20190094221
    Abstract: Methods, compositions and kits for detecting Group A streptococcus in a biological sample are described. More particularly, the present disclosure provides an immunoassay in which the specificity of detection of Group A streptococcus is enhanced by addition of N-acetyl-D-glucosamine. These methods, compositions and kits are useful in convenient, reliable and early diagnosis of streptococcal infection in a human subject.
    Type: Application
    Filed: November 28, 2018
    Publication date: March 28, 2019
    Inventors: Peter Yan-Guo REN, Jason MCCLURE, Kevin S. RICHARDSON
  • Patent number: 10185606
    Abstract: Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: January 22, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: Peter Yan, Alan Gatherer, Alex Elisa Chandra, Lee Dobson Mcfearin, Mark Brown, Debashis Bhattacharya, Fang Yu, Xingfeng Chen, Yan Bei, Ke Ning, Chushun Huang, Tong Sun, Xiaotao Chen
  • Patent number: 10168329
    Abstract: Methods, compositions and kits for detecting Group A streptococcus in a biological sample are described. More particularly, the present disclosure provides an immunoassay in which the specificity of detection of Group A streptococcus is enhanced by addition of N-acetyl-D-glucosamine. These methods, compositions and kits are useful in convenient, reliable and early diagnosis of streptococcal infection in a human subject.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: January 1, 2019
    Assignee: Quidel Corporation
    Inventors: Peter Yan-Guo Ren, Jason McClure, Kevin S. Richardson
  • Publication number: 20180321939
    Abstract: Technology for providing data to a processing unit is disclosed. A computer processor may be divided into a master processing unit and consumer processing units. The master processing unit at least partially decodes a machine instruction and determines whether data is needed to execute the machine instruction. The master processing unit sends a request to memory for the data. The request may indicate that the data is to be sent from the memory to a consumer processing unit. The data sent by the memory in response to the request may be stored in local read storage that is close to the consumer processing unit for fast access. The master processing unit may also provide the machine instruction to the consumer processing unit. The consumer processing unit may access the data from the local read storage and execute the machine instruction based on the accessed data.
    Type: Application
    Filed: May 4, 2017
    Publication date: November 8, 2018
    Applicant: Futurewei Technologies, Inc.
    Inventors: Alan Gatherer, Sushma Wokhlu, Peter Yan, Ywhpyng Harn, Ashish Rai Shrivastava, Tong Sun, Lee Dobson McFearin
  • Publication number: 20170293512
    Abstract: Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.
    Type: Application
    Filed: April 12, 2016
    Publication date: October 12, 2017
    Inventors: Peter Yan, Alan Gatherer, Alex Elisa Chandra, Lee Dobson Mcfearin, Mark Brown, Debashis Bhattacharya, Fang Yu, Xingfeng Chen, Yan Bei, Ke Ning, Chushun Huang, Tong Sun, Xiaotao Chen
  • Publication number: 20170293587
    Abstract: A described embodiment of the present invention includes a network having a first, second an d third plurality of routers connected to a plurality of endpoints. At least one of the first plurality of routers includes a plurality of interposers having a number of queues. The at least one of the first plurality of routers has a demultiplexer for each interposer configured to receive multiplexed data from the interposer and provide demultiplexed data on to a plurality of second queues corresponding to the first queues of the number of queues. The at least one of the first plurality of routers also includes a number multiplexers, each of the number multiplexers having inputs configured to receive data from the number of queues.
    Type: Application
    Filed: April 12, 2016
    Publication date: October 12, 2017
    Inventors: Peter Yan, Alex Elisa Chandra, YwhPyng Harn, Xiaotao Chen, Alan Gatherer, Fang Yu, Xingfeng Chen, Zhuolei Wang, Yang Zhou
  • Publication number: 20170293586
    Abstract: Disclosed is method for operating an interposer that includes assigning a binary port weight to a plurality of input ports of the interposer. The sum of all of the port weights is less than or equal to a number of traversals available to the interposer in a cycle. A traversal counter is set zero at the beginning of each cycle. The output of the traversal counter is a binary number of m bits. A mask is generated when a bit of the traversal counter transitions from a zero to a one. The mask is generated having the m?k+1 bit of the mask equal to one and all other bits of the mask equal to zero. Data is transmitted from each port when both the binary port weight and the mask have a one in the same bit position.
    Type: Application
    Filed: April 12, 2016
    Publication date: October 12, 2017
    Inventors: Peter Yan, Alex Elisa Chandra, Lee Dobson McFearin, Fang Yu, Alan Gatherer
  • Patent number: 9448617
    Abstract: System and method embodiments are provided for messaging-based System-on-a-chip (SoC) power gating. The embodiments enable fine granularity SoC power gating without introducing significant latency and substantially maximizes SoC power reduction. In an embodiment, a method in a first SoC resource for messaging-based power gating includes receiving at the first SoC resource a wakeup notification message (WNM) from a second SoC resource, wherein the WNM comprises a time at which a result message from the second SoC resource is expected to arrive at the first SoC resource; determining with the first SoC resource a wake-up time according to the time at which the result message from the second SoC resource is expected to arrive at the first SoC resource; setting a wake-up time timer to expire at the wake-up time; and waking up the first SoC resource when the wake-up time timer expires when the first SoC resource is asleep.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: September 20, 2016
    Assignee: Futurewei Technologies, Inc.
    Inventors: Mark Brown, Mehran Bagheri, Peter Yan, Alan Gatherer
  • Publication number: 20150261290
    Abstract: System and method embodiments are provided for messaging-based System-on-a-chip (SoC) power gating. The embodiments enable fine granularity SoC power gating without introducing significant latency and substantially maximizes SoC power reduction. In an embodiment, a method in a first SoC resource for messaging-based power gating includes receiving at the first SoC resource a wakeup notification message (WNM) from a second SoC resource, wherein the WNM comprises a time at which a result message from the second SoC resource is expected to arrive at the first SoC resource; determining with the first SoC resource a wake-up time according to the time at which the result message from the second SoC resource is expected to arrive at the first SoC resource; setting a wake-up time timer to expire at the wake-up time; and waking up the first SoC resource when the wake-up time timer expires when the first SoC resource is asleep.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 17, 2015
    Applicant: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Mark Brown, Mehran Bagheri, Peter Yan, Alan Gatherer
  • Publication number: 20130196337
    Abstract: Methods, compositions and kits for detecting Group A streptococcus in a biological sample are described. More particularly, the present disclosure provides an immunoassay in which the specificity of detection of Group A streptococcus is enhanced by addition of N-acetyl-D-glucosamine. These methods, compositions and kits are useful in convenient, reliable and early diagnosis of streptococcal infection in a human subject.
    Type: Application
    Filed: July 31, 2012
    Publication date: August 1, 2013
    Applicant: Quidel Corporation
    Inventors: Peter Yan-Guo Ren, Jason McClure, Kevin S. Richardson
  • Patent number: 8215791
    Abstract: An illuminating headlamp consisting of a headband and at least one optical device providing illumination at a known distance from said optical device attached to said headband. Each optical device consists of a housing having an open first end and an open second end. There is a light emitting device attached to a mounting which is attached to the second end causing said light emitting device to be orientated at a known angle to an axis of said housing. At least one optically transparent lens is incorporated into said first end, and a means for adjusting said optically transparent lens in order to cause a focal point of the lens to be positioned behind said light emitting device, wherein a zone of substantially uniform illumination is projected at said known distance.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: July 10, 2012
    Assignee: Designs for Vision, Inc.
    Inventors: Richard E. Feinbloom, Kenneth Braganca, Peter Yan
  • Patent number: D874463
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: February 4, 2020
    Assignees: TODA KOGYO CORP., SECURITAG ASSEMBLY GROUP CO., LTD.
    Inventors: Jun Koujima, Mark Chang, Yoshiteru Kouno, Peter Yan
  • Patent number: D890007
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: July 14, 2020
    Assignees: TODA KOGYO CORP., SECURITAG ASSEMBLY GROUP CO., LTD.
    Inventors: Jun Koujima, Mark Chang, Yoshiteru Kouno, Peter Yan
  • Patent number: D894773
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: September 1, 2020
    Assignees: TODA KOGYO CORP., SECURITAG ASSEMBLY GROUP CO., LTD.
    Inventors: Jun Koujima, Mark Chang, Yoshiteru Kouno, Peter Yan