Patents by Inventor Peter Yan-Tek Hsu

Peter Yan-Tek Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Alignment and Ordering of Vector Elements for Single Instruction Multiple Data Processing
    Publication number: 20110055497
    Abstract: The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register.
    Type: Application
    Filed: September 3, 2010
    Publication date: March 3, 2011
    Applicant: MIPS Technologies, Inc.
    Inventors: Timothy J. VAN HOOK, Peter Yan-Tek Hsu, William A. Huffman, Henry P. Moreton, Earl A. Killian
  • Alignment and ordering of vector elements for single instruction multiple data processing
    Patent number: 7793077
    Abstract: The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: September 7, 2010
    Assignee: MIPS Technologies, Inc.
    Inventors: Timothy J. Van Hook, Peter Yan-Tek Hsu, William A. Huffman, Henry P. Moreton, Earl A. Killian