Abstract: A method of measuring signal delay in a integrated circuit comprising applying a common clock signal at a circuit input and output, applying a test signal at the circuit input, detecting a corresponding output signal at the circuit output and detecting whether the test signal and output signal occur in a common part of the clock signal.

Abstract: A system may include an apparatus for defrosting and/or clearing debris from a refrigeration component using pressurized dry air. The apparatus may include an air compressor that generates pressurized air. The air may be filtered (before or after compressing) to remove moisture and/or other contaminants to thereby generate pressurized dry air. The apparatus may include a reservoir, coupled to the air compressor, for storing the pressurized dry air. The reservoir may be coupled to one or more air distribution manifolds coupled to the reservoir. Each of the one or more air distribution manifolds may be coupled to an air discharge component such as an air pipe or tube. The air discharge component may receive the pressurized air from the air exhaust and may discharge the pressurized air through a plurality of orifices to the refrigeration component thereby defrosting and/or clearing debris from the refrigeration component.

Abstract: A method of measuring signal delay in a integrated circuit comprising applying a common clock signal at a circuit input and output, applying a test signal at the circuit input, detecting a corresponding output signal at the circuit output and detecting whether the test signal and output signal occur in a common part of the clock signal.

Abstract: A method of generating a user circuit implementation for programming a PLD comprising generating a set of user circuit implementation configuration candidates, measuring one or more characteristics of the PLD in a measurement phase and selecting a user circuit implementation from the set of candidates based on a measured characteristic.

Abstract: Capacitor area is increased in the vertical direction by forming capacitors on topographic features on the chip. The features are formed during existing process steps. Adding vertical topography increases capacitance per unit area, reducing die size at no added development cost or mask steps.

Abstract: Capacitor area is increased in the vertical direction by forming capacitors on topographic features on the chip. The features are formed during existing process steps. Adding vertical topography increases capacitance per unit area, reducing die size at no added development cost or mask steps.

Abstract: This invention provides a logic block comprising an mxn array of partial calculating circuits (where m≧2 and n≧2) operable to generate partial product components of an m-bit multiplicand x n-bit multiplicand binary multiplication and to generate a cumulative sum of the partial products for each bit of one of the multiplicands. A configurable output circuit which is operable under the control of a configuration signal either (a) to sum the cumulative sums of partial products generated by the partial calculating circuits so as to generate a product value, or (b) to pass data representing the cumulative sums of the partial product components to partial calculating circuits within one or more further logic blocks. Also provided is a logic circuit including two or more such logic blocks, data interconnections for data transfer between the logic blocks and control interconnections for control signal transfer to the logic blocks.

Abstract: A method for fabricating a BiCMOS integrated circuit. The method includes the steps of forming in a single implantation step a base region 211 of a bipolar transistor and a p-well 212 of an n-channel MOS transistor; and forming in a single implantation step a collector contact well 213 of a bipolar transistor and an n-well 208 of a p-channel MOS transistor.

Abstract: This is a system and method of in-situ coating, baking and curing of dielectric material. The system may include: dispensing apparatus for dispensing spin-on material; a lamp module 50; a window 54 connected to the lamp module 50; an environmental control chamber 56 connected to the window 54; an access gate 60 for wafers 58 in the environmental control chamber 56; a spin chuck 62 inside the environmental control chamber 56; and an exhaust pipe 64 connected to the environmental control chamber 56. The lamp module 50 may contains infra red and ultra violet lamps. In addition, the coating chamber may process dielectric material such as spin-on glass, silicon dioxide and various other spin-on material.

Abstract: The described embodiments of the present invention provide DRAM cells, structures and manufacturing methods. In a first embodiment, a DRAM cell with a trench capacitor having a first plate formed as a diffusion on the outside surface of a trench formed in the substrate and a second plate having a conductive region formed inside the trench is fabricated. In another embodiment of the present invention, a planar capacitor is used with a field plate isolation scheme including a transfer transistor moat region self-aligned to the field plate. This structure allows the elimination of alignment tolerances between the capacitor and the transistor thus reducing the space necessary between the transistor and the capacitor.In another embodiment of the present invention, a memory cell using two conductive plates formed inside a trench as the storage capacitor is fabricated.