Abstract: Capacitor area is increased in the vertical direction by forming capacitors on topographic features on the chip. The features are formed during existing process steps. Adding vertical topography increases capacitance per unit area, reducing die size at no added development cost or mask steps.

Abstract: Capacitor area is increased in the vertical direction by forming capacitors on topographic features on the chip. The features are formed during existing process steps. Adding vertical topography increases capacitance per unit area, reducing die size at no added development cost or mask steps.

Abstract: A method for fabricating a BiCMOS integrated circuit. The method includes the steps of forming in a single implantation step a base region 211 of a bipolar transistor and a p-well 212 of an n-channel MOS transistor; and forming in a single implantation step a collector contact well 213 of a bipolar transistor and an n-well 208 of a p-channel MOS transistor.

Abstract: This is a system and method of in-situ coating, baking and curing of dielectric material. The system may include: dispensing apparatus for dispensing spin-on material; a lamp module 50; a window 54 connected to the lamp module 50; an environmental control chamber 56 connected to the window 54; an access gate 60 for wafers 58 in the environmental control chamber 56; a spin chuck 62 inside the environmental control chamber 56; and an exhaust pipe 64 connected to the environmental control chamber 56. The lamp module 50 may contains infra red and ultra violet lamps. In addition, the coating chamber may process dielectric material such as spin-on glass, silicon dioxide and various other spin-on material.

Abstract: The described embodiments of the present invention provide DRAM cells, structures and manufacturing methods. In a first embodiment, a DRAM cell with a trench capacitor having a first plate formed as a diffusion on the outside surface of a trench formed in the substrate and a second plate having a conductive region formed inside the trench is fabricated. In another embodiment of the present invention, a planar capacitor is used with a field plate isolation scheme including a transfer transistor moat region self-aligned to the field plate. This structure allows the elimination of alignment tolerances between the capacitor and the transistor thus reducing the space necessary between the transistor and the capacitor.In another embodiment of the present invention, a memory cell using two conductive plates formed inside a trench as the storage capacitor is fabricated.