Patents by Inventor Peter Zdebel

Peter Zdebel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080012137
    Abstract: In one embodiment, a pair of sidewall passivated trench contacts is formed in a substrate to provide electrical contact to a sub-surface feature. A doped region is diffused between the pair of sidewall passivated trenches to provide low resistance contacts.
    Type: Application
    Filed: June 27, 2007
    Publication date: January 17, 2008
    Inventors: Gordon Grivna, Peter Zdebel
  • Publication number: 20070034947
    Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.
    Type: Application
    Filed: October 19, 2006
    Publication date: February 15, 2007
    Inventors: Gary Loechelt, John Parsey, Peter Zdebel, Gordon Grivna
  • Publication number: 20060261444
    Abstract: In one embodiment, a pair of sidewall passivated trench contacts is formed in a substrate to provide electrical contact to a sub-surface feature. A doped region is diffused between the pair of sidewall passivated trenches to provide low resistance contacts.
    Type: Application
    Filed: May 20, 2005
    Publication date: November 23, 2006
    Inventors: Gordon Grivna, Peter Zdebel
  • Publication number: 20060246652
    Abstract: A method of forming a semiconductor device includes forming isolation trenches that are used to isolate some of the electrical elements such as transistors, diodes, capacitors, or resistors on a semiconductor die from other elements on the semiconductor die.
    Type: Application
    Filed: May 2, 2005
    Publication date: November 2, 2006
    Inventors: Gordon Grivna, Peter Zdebel, Diann Dow
  • Publication number: 20060240625
    Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a counter-doped drain region spaced apart from a channel region.
    Type: Application
    Filed: April 25, 2005
    Publication date: October 26, 2006
    Inventors: Gary Loechelt, Peter Zdebel
  • Publication number: 20060237780
    Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a screening electrode spaced apart from a channel region.
    Type: Application
    Filed: April 25, 2005
    Publication date: October 26, 2006
    Inventors: Gary Loechelt, Peter Zdebel
  • Publication number: 20060180857
    Abstract: In one embodiment, an edge termination structure is formed in a semiconductor layer of a first conductivity type. The termination structure includes an isolation trench and a conductive layer in contact with the semiconductor layer. The semiconductor layer is formed over a semiconductor substrate of a second conductivity type. In a further embodiment, the isolation trench includes a plurality of shapes that comprise portions of the semiconductor layer.
    Type: Application
    Filed: February 15, 2005
    Publication date: August 17, 2006
    Inventors: Gary Loechelt, Peter Zdebel, Gordon Grivna
  • Publication number: 20060180947
    Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.
    Type: Application
    Filed: February 15, 2005
    Publication date: August 17, 2006
    Inventors: Gary Loechelt, Peter Zdebel, Gordon Grivna
  • Publication number: 20060180858
    Abstract: In one embodiment, a charge compensation region is formed in a body of semiconductor material. A conductive layer is coupled to the charge compensation layer. In a further embodiment, the charge compensation region comprises a trench filled with opposite conductivity type semiconductor layers.
    Type: Application
    Filed: February 15, 2005
    Publication date: August 17, 2006
    Inventors: Gary Loechelt, Peter Zdebel, Gordon Grivna
  • Publication number: 20050145945
    Abstract: In one embodiment, a concentric ring ESD structure includes a first p-type region and a second p-type region are formed in a layer of semiconductor material. The two p-type regions are coupled together with a floating n-type buried layer. The first and second p-type regions form a back-to-back diode structure with the floating n-type buried layer. A pair of shorted n-type and p-type contact regions is formed in each of the first and second regions. An isolation region is formed between the first and second p-type regions.
    Type: Application
    Filed: January 2, 2004
    Publication date: July 7, 2005
    Inventors: Peter Zdebel, Diann Dow